A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC.
Wei ZhouYue NiuXiaocong LianXin ZhouJiamin YangPublished in: PCM (1) (2016)
Keyphrases
- intra prediction
- vlsi architecture
- mode decision
- video compression
- low complexity
- spatial correlation
- coding efficiency
- vlsi implementation
- pixel wise
- low power
- macroblock
- real time
- video transmission
- video coding standard
- motion compensation
- rate distortion
- motion vectors
- bit rate
- motion estimation
- distributed video coding
- video streaming
- image compression
- wavelet transform
- computer vision