Yasushi Yuminaka

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 22

Top Topics

Data Transmission

Quality Evaluation

Top Venues

IEICE Trans. Inf. Syst.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Yasushi Yuminaka
Foreword. IEICE Trans. Inf. Syst. 107 (8) (2024)
Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka
Evaluation of Multi-Valued Data Transmission in Two-Dimensional Symbol Mapping using Linear Mixture Model. IEICE Trans. Inf. Syst. 107 (8) (2024)
Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima
Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols. IEICE Trans. Inf. Syst. 107 (8) (2024)
Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima
PAM-4 Data Transmission Quality Evaluation Using Two- and Three-Dimensional Mapping of Received Symbols. ISMVL (2023)
Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka
Evaluation and Symbol Classification of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping with Linear Mixture Model. ISMVL (2023)
Kazuharu Nakajima, Yasushi Yuminaka, Yosuke Iijima
Multi-Valued Data Transmission Quality Evaluation Using Two-Dimensional PAM-4 Symbol Mapping. FLAP 10 (6) (2023)
Yosuke Iijima, Yasushi Yuminaka
Efficient PAM-4 Symbol Estimation Using Soft Clustering. FLAP 9 (3) (2022)
Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka
Two-Dimensional Symbol Mapping for Evaluating Multi-Valued Data Transmission Quality. ISMVL (2022)
Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN (2022)
Yosuke Iijima, Keigo Taya, Yasushi Yuminaka
PAM-4 Eye-Opening Monitor Technique Using Gaussian Mixture Model for Adaptive Equalization. IEICE Trans. Inf. Syst. (8) (2021)
Yosuke Iijima, Yasushi Yuminaka
Efficient PAM-4 Data Transmission with Closed Eye Using Symbol Distribution Estimation. ISMVL (2021)
Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) (2021)
Yosuke Iijima, Keigo Taya, Yasushi Yuminaka
PAM-4 Eye-Opening Monitoring Techniques Using Gaussian Mixture Model. ISMVL (2020)
Yasushi Yuminaka, Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima
PAM-4 Signal Transmitter using FPGA and DAC for Serial-link Test. FLAP 7 (1) (2020)
Keigo Taya, Yasushi Yuminaka, Yosuke Iijama
Statistical Waveform Evaluation Method for Adaptive PAM-4 Equalization. FLAP 8 (5) (2020)
Yosuke Iijima, Yasushi Yuminaka
Waveform Shaping Transmitter Combining Digital and Analog Circuits for Multi - Valued Signaling. ISMVL (2019)
Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima, Yasushi Yuminaka
Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test. ISMVL (2018)
Yosuke Iijima, Yasushi Yuminaka
Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission. IEICE Trans. Inf. Syst. (8) (2017)
Yasushi Yuminaka, Takuya Kitamura, Yosuke Iijima
PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions. ISMVL (2017)
Yosuke Iijima, Yasushi Yuminaka
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission. ISMVL (2016)
Yasushi Yuminaka, Yosuke Iijima
Multiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Yasushi Yuminaka, Yuuki Takada, Tomonao Okada
Comparison of Spectrally Efficient Coding Techniques for High-Speed VLSI Data Transmission. J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Yosuke Iijima, Yuki Takada, Yasushi Yuminaka
High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding. IEICE Trans. Inf. Syst. (9) (2014)
Yosuke Iijima, Yasushi Yuminaka
Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding. ISMVL (2014)
Yasushi Yuminaka, Yuki Takada, Tomonao Okada, Yosuke Iijima
Comparison of Spectrally Efficient Coding Techniques for High-Speed Serial Links. ISMVL (2014)
Yasushi Yuminaka, Kyohei Kawano
A Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Yasushi Yuminaka, Masaaki Okui
Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation. ISMVL (2012)
Yasushi Yuminaka, Kyohei Kawano
A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface. ISMVL (2010)
Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi
Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques. IEICE Trans. Inf. Syst. (8) (2010)
Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. ISMVL (2009)
Yasushi Yuminaka, Yasunori Takahashi
Time-Domain Pre-Emphasis Techniques for Multiple Valued Data Transmission. J. Multiple Valued Log. Soft Comput. 15 (4) (2009)
Yasushi Yuminaka, Yasunori Takahashi
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. ISMVL (2008)
Yasushi Yuminaka, Kazuyoshi Yamamura
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
Yasushi Yuminaka, Kazuyoshi Yamamura
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. ISMVL (2007)
Yasushi Yuminaka
Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing. J. Multiple Valued Log. Soft Comput. 11 (5-6) (2005)
Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. ISMVL (2002)
Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. ISMVL (2000)
Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San, Yoshitaka Onaya, Yasuyuki Kimura, Yasushi Yuminaka, Yoshisato Sasaki, Kouji Tanaka, Fuminori Abe
A high-speed CMOS track/hold circuit. ICECS (1999)
Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. ISMVL (1998)
Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. ISMVL (1996)
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. ISMVL (1994)
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
Design of Set-Valued Logic Networks for Wave-Parallel Computing. ISMVL (1993)
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. ISMVL (1991)