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Ward S. Titus
Publication Activity (10 Years)
Years Active: 2006-2014
Publications (10 Years): 0
Top Topics
Historical Data
Linear Systems
Dual Channel
Intel Xeon
Top Venues
CICC
IEEE J. Solid State Circuits
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Publications
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Jeremy Walker
,
John G. Kenney
,
Jesse Bankman
,
Terry Chen
,
Steve Harston
,
Kenneth Lawas
,
Andrew Lewine
,
Richard Soenneker
,
Michael St. Germain
,
Ward S. Titus
,
Andrew Y. Wang
,
Kimo Tam
A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS.
CICC
(2014)
Jack Kenney
,
Terry Chen
,
Larry DeVito
,
Declan Dalton
,
Stuart McCracken
,
Richard Soenneker
,
Ward S. Titus
,
Todd S. Weigandt
A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery.
CICC
(2014)
Ward S. Titus
,
John G. Kenney
A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs.
IEEE J. Solid State Circuits
47 (5) (2012)
Jack Kenney
,
Declan Dalton
,
Murat Hayri Eskiyerli
,
Eric Evans
,
Barry Hilton
,
Dave Hitchcox
,
Terence Kwok
,
Daniel Mulcahy
,
Chris McQuilkin
,
Viswabharath Reddy
,
Siva Selvanayagam
,
Paul Shepherd
,
Ward S. Titus
,
Larry DeVito
A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS.
ISSCC
(2006)
John G. Kenney
,
Declan Dalton
,
Eric Evans
,
Murat Hayri Eskiyerli
,
Barry Hilton
,
Dave Hitchcox
,
Terence Kwok
,
Daniel Mulcahy
,
Chris McQuilkin
,
Viswabharath Reddy
,
Siva Selvanayagam
,
Paul Shepherd
,
Ward S. Titus
,
Lawrence DeVito
A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS.
IEEE J. Solid State Circuits
41 (12) (2006)