Declan Dalton

Publication Activity (10 Years)

Years Active: 1999-2022
Publications (10 Years): 1

Top Topics

Root Mean Square

Top Venues

Publications

Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time. ISSCC (2022)
Jack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt
A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. CICC (2014)
Jack Kenney, Declan Dalton, Murat Hayri Eskiyerli, Eric Evans, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Larry DeVito
A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS. ISSCC (2006)
John G. Kenney, Declan Dalton, Eric Evans, Murat Hayri Eskiyerli, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Lawrence DeVito
A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS. IEEE J. Solid State Circuits 41 (12) (2006)
Declan Dalton, Kwet Chai, Eric Evans, Mark A. Ferriss, Dave Hitchcox, Paul Murray, Sivanendra Selvanayagam, Paul Shepherd, Lawrence DeVito
A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. IEEE J. Solid State Circuits 40 (12) (2005)
Iuri Mehr, Declan Dalton
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications. IEEE J. Solid State Circuits 34 (7) (1999)