Valentin Muresan

Publication Activity (10 Years)

Years Active: 2000-2016
Publications (10 Years): 1

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Valentin Muresan
Superior vision: Always on human-like vision for intelligent devices. SACI (2016)
Valentin Stangaciu, Georgiana Macariu, Mihai V. Micea, Valentin Muresan, Brendan Barry
Requirements of a real-time multiprocessor operating system for multimedia applications. SACI (2011)
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm. EvoWorkshops (2006)
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. ISCAS (2006)
Daniel Larkin, Andrew Kinane, Valentin Muresan, Noel E. O'Connor
An Efficient Hardware Architecture for a Neural Network Activation Function Generator. ISNN (2) (2006)
Daniel Larkin, Valentin Muresan, Noel E. O'Connor
A low complexity hardware architecture for motion estimation. ISCAS (2006)
Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. FPT (2005)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. J. Electron. Test. 20 (1) (2004)
Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. PATMOS (2004)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. IEEE International Workshop on Rapid System Prototyping (2001)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. VTS (2000)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Power-Constrained Block-Test List Scheduling. IEEE International Workshop on Rapid System Prototyping (2000)
Valentin Muresan, Xiaojun Wang, Mircea Vladutiu
The left edge algorithm in block test scheduling under power constraints. ISCAS (2000)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
A comparison of classical scheduling approaches in power-constrained block-test scheduling. ITC (2000)
Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Asian Test Symposium (2000)