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Tresa Joseph
ORCID
Publication Activity (10 Years)
Years Active: 2021-2024
Publications (10 Years): 5
Top Topics
Hardware Implementation
Hardware Architecture
Recurrent Neural Networks
Singular Value Decomposition
Top Venues
Circuits Syst. Signal Process.
IEEE Comput. Archit. Lett.
VDAT
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
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Publications
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Mrinmay Sasmal
,
Tresa Joseph
,
T. S. Bindiya
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI.
IEEE Comput. Archit. Lett.
23 (1) (2024)
Tresa Joseph
,
T. S. Bindiya
Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM.
Circuits Syst. Signal Process.
42 (11) (2023)
Tresa Joseph
,
T. S. Bindiya
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
42 (12) (2023)
Tresa Joseph
,
T. S. Bindiya
Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders.
Circuits Syst. Signal Process.
42 (12) (2023)
Tresa Joseph
,
T. S. Bindiya
High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network.
VDAT
(2021)