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Thejas Kempanna
Publication Activity (10 Years)
Years Active: 2016-2018
Publications (10 Years): 2
Top Topics
Memory Usage
Classical Logic
Wide Range
Worst Case
Top Venues
VLSI Circuits
IEEE J. Solid State Circuits
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Publications
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Balaji Jayaraman
,
Derek Leu
,
Janakiraman Viraraghavan
,
Alberto Cestero
,
Ming Yin
,
John Golz
,
Rajesh Reddy Tummuru
,
Ramesh Raghavan
,
Dan Moy
,
Thejas Kempanna
,
Faraz Khan
,
Toshiaki Kirihata
,
Subramanian S. Iyer
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits
53 (3) (2018)
Janakiraman Viraraghavan
,
Derek Leu
,
Balaji Jayaraman
,
Alberto Cestero
,
Robert Kilker
,
Ming Yin
,
John Golz
,
Rajesh Reddy Tummuru
,
Ramesh Raghavan
,
Dan Moy
,
Thejas Kempanna
,
Faraz Khan
,
Toshiaki Kirihata
,
Subramanian S. Iyer
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
VLSI Circuits
(2016)