80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Janakiraman ViraraghavanDerek LeuBalaji JayaramanAlberto CesteroRobert KilkerMing YinJohn GolzRajesh Reddy TummuruRamesh RaghavanDan MoyThejas KempannaFaraz KhanToshiaki KirihataSubramanian S. IyerPublished in: VLSI Circuits (2016)