Tapani Ahonen

Publication Activity (10 Years)

Years Active: 2003-2017
Publications (10 Years): 6

Top Topics

Fourier Transform

Fpga Implementation

Memory Management

Top Venues

J. Signal Process. Syst.

J. Syst. Archit.

Publications

Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. J. Signal Process. Syst. 87 (3) (2017)
Farid Shamani, Vida Fakour Sevom, Tapani Ahonen, Jari Nurmi
Integration issues of a run-time configurable memory management unit to a RISC processor on FPGA. Microprocess. Microsystems 49 (2017)
Farid Shamani, Roberto Airoldi, Vida Fakour Sevom, Tapani Ahonen, Jari Nurmi
FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios. J. Syst. Archit. 76 (2017)
Waqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms. J. Signal Process. Syst. 85 (3) (2016)
Farid Shamani, Vida Fakour Sevom, Tapani Ahonen, Jari Nurmi
FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor. NORCAS (2016)
Kui Wang, Jari Nurmi, Tapani Ahonen
Accelerating Computation on an Android Phone with OpenCL Parallelism and Optimizing Workload Distribution between a Phone and a Cloud Service. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld (2016)
Farid Shamani, Vida Fakour Sevom, Jari Nurmi, Tapani Ahonen
Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA. NORCAS (2015)
Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
Design of a hybrid multicore platform for high performance reconfigurable computing. NORCAS (2015)
Farid Shamani, Roberto Airoldi, Tapani Ahonen, Jari Nurmi
FPGA implementation of a flexible synchronizer for cognitive radio applications. DASIP (2014)
Omer Anjum, Tapani Ahonen, Jari Nurmi
MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver. J. Syst. Archit. 60 (1) (2014)
Waqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. ASAP (2014)
Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array. ISSoC (2014)
Guoqing Zhang, Tapani Ahonen
A LLVM based compiler for COFFEE. ISORC (2013)
Rizwan Fazal, Waqar Hussain, Tapani Ahonen, Jari Nurmi
Evaluation of WCDMA receiver baseband processing on a Multi-Processor System-On-Chip. DSP (2013)
Waqar Hussain, Fabio Garzia, Tapani Ahonen, Jari Nurmi
Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems. J. Signal Process. Syst. 69 (2) (2012)
Leyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi, Tapani Ahonen
Reconfigurable multi-processor architecture for streaming applications. FPL (2012)
Waqar Hussain, Tapani Ahonen, Jari Nurmi
Effects of scaling a coarse-grain reconfigurable array on power and energy consumption. ISSoC (2012)
Waqar Hussain, Tapani Ahonen, Roberto Airoldi, Jari Nurmi
Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators. ReCoSoC (2012)
Waqar Hussain, Tapani Ahonen, Fabio Garzia, Jari Nurmi
Application-driven dimensioning of a Coarse-Grain Reconfigurable Array. AHS (2011)
Roberto Airoldi, Tapani Ahonen, Fabio Garzia, Dragomir Milojevic, Jari Nurmi
Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC. J. Signal Process. Syst. 64 (1) (2011)
Omer Anjum, Tapani Ahonen, Fabio Garzia, Jari Nurmi, Claudio Brunelli, Heikki Berg
State of the art baseband DSP platforms for Software Defined Radio: A survey. EURASIP J. Wirel. Commun. Netw. 2011 (2011)
Heikki Hurskainen, Jussi Raasakka, Tapani Ahonen, Jari Nurmi
Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing. EURASIP J. Embed. Syst. 2009 (2009)
Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. SAMOS (2009)
Fabio Garzia, Roberto Airoldi, Tapani Ahonen, Jari Nurmi, Dragomir Milojevic
Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios. SiPS (2009)
Claudio Brunelli, Fabio Campi, Claudio Mucci, Davide Rossi, Tapani Ahonen, Juha Kylliäinen, Fabio Garzia, Jari Nurmi
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications. J. Syst. Archit. 54 (12) (2008)
Xin Wang, Tapani Ahonen, Jari Nurmi
Applying CDMA Technique to Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Xin Wang, Tapani Ahonen, Jari Nurmi
Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. FPL (2006)
Tapani Ahonen, Jari Nurmi
Integration of a NoC-Based Multimedia Processing Platform. FPL (2005)
Xin Wang, Tapani Ahonen, Jari Nurmi
A synthesizable RTL design of asynchronous FIFO. SoC (2004)
Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi
Topology optimization for application-specific networks-on-chip. SLIP (2004)
Tapani Ahonen, Jari Nurmi
Design reuse and design for reuse, a case study on HDSL2. SoC (2004)
David A. Sigüenza-Tortosa, Tapani Ahonen, Jari Nurmi
Issues in the development of a practical NoC: the Proteo concept. Integr. 38 (1) (2004)
Tapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho
Block-wise Extraction of Rent's Exponents for an Extensible Processor. ISVLSI (2003)