Syed Zahid Ahmed

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 5

Top Topics

Image Compression

High Frame Rate

Fpga Implementation

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Mohammed Shaaban Ibraheem, Khalil Hachicha, Syed Zahid Ahmed, Laurent Lambert, Patrick Garda
High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform. J. Real Time Image Process. 16 (6) (2019)
Laurent Lambert, Syed Zahid Ahmed, Khalil Hachicha, Andréa Pinna, Patrick Garda
High frame rate medical quality video compression for tele-EEG. EMBC (2016)
Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda
A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only). FPGA (2016)
Mohammed Shaaban Ibraheem, Khalil Hachicha, Syed Zahid Ahmed, Sylvain Hochberg, Patrick Garda
Logarithmic Discrete Wavelet Transform for Medical Image Compression with Diagnostic Quality. EAI Endorsed Trans. Pervasive Health Technol. 2 (8) (2016)
Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda
Medical images compression with clinical diagnostic quality using logarithmic DWT. BHI (2016)
Laurent Lambert, Khalil Hachicha, Syed Zahid Ahmed, Andréa Pinna, Patrick Garda
Synchronizing physiological data and video in a telemedicine application: A multimedia approach. EMBC (2015)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree. ACM Trans. Reconfigurable Technol. Syst. 9 (1) (2015)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
Fast and Power Efficient Heapsort IP for Image Compression Application. FCCM (2014)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only). FPGA (2014)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access. ARC (2014)
Yuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding. VLSI-SoC (2013)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
Design and analysis of an FPGA based encoder SoC for locally stationary image source. DASIP (2013)
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source. FPL (2013)
Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs. FPL (2010)
Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed
A Dynamic Reconfigurable MRAM based FPGA. ERSA (2010)
Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. ReConFig (2009)
Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. DATE (2009)
Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. ReConFig (2008)