Sign in
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding.
Yuhui Bai
Syed Zahid Ahmed
Imen Mhedhbi
Khalil Hachicha
Cedric Champion
Patrick Garda
Bertrand Granado
Published in:
VLSI-SoC (2013)
Keyphrases
</>
congestion control
signal processing
digital signal processing
real time image processing
verilog hdl
coding scheme
high speed
digital signal
real time
coding method
systolic array
hierarchical structure
power consumption
power reduction
digital signal processors