Login / Signup

Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.

Syed Zahid AhmedJulien EydouxLaurent RougeJean-Baptiste CuelleGilles SassatelliLionel Torres
Published in: DATE (2009)
Keyphrases
  • parallel processing
  • high speed
  • parallel architecture
  • power reduction
  • graphical models
  • power consumption
  • language learning
  • computer architecture