Sucheta Mohapatra

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 3

Top Topics

Optimization Scheme

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske
Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
Performance optimization and power efficiency in 3D IC with buffer insertion scheme. SoCC (2016)
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
Buffered Interconnects in 3D IC Layout Design. SLIP (2016)
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
Dynamic nets-to-TSVs assignment in 3D floorplanning. ISCAS (2015)
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
3D floorplanning with nets-to-TSVs assignment. ICECS (2014)