Satya K. Vendra

Publication Activity (10 Years)

Years Active: 2018-2021
Publications (10 Years): 3

Top Topics

Integrated Circuit

Evaluation Methods

Power Dissipation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske
Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Satya K. Vendra, Malgorzata Chrzanowska-Jeske
Fast Thermal Goodness Evaluation of a 3D-IC Floorplan. ISQED (2021)
Satya K. Vendra, Malgorzata Chrzanowska-Jeske
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. ISCAS (2018)