Stuart Fiske

Publication Activity (10 Years)

Years Active: 1988-2009
Publications (10 Years): 0

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Chris Rowen, Peter R. Nuth, Stuart Fiske
A DSP architecture optimized for wireless baseband. SoC (2009)
William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
Retrospective: the J-machine. 25 Years ISCA: Retrospectives and Reprints (1998)
Stuart Fiske, William J. Dally
Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. HPCA (1995)
Stuart Fiske, William J. Dally
Thread prioritization: A thread scheduling mechanism for multiple-context parallel processors. Future Gener. Comput. Syst. 11 (6) (1995)
William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
The Message Driven Processor: An Integrated Multicomputer Processing Element. ICCD (1992)
William J. Dally, Stuart Fiske, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Roy E. Davison, Gregory A. Fyler
The message-driven processor: a multicomputer processing node with efficient mechanisms. IEEE Micro 12 (2) (1992)
William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills
The J-Machine: A Fine-Gain Concurrent Computer. IFIP Congress (1989)
Stuart Fiske, William J. Dally
The Reconfigurable Arithmetic Processor. ISCA (1988)