Siddika Berna Örs

Publication Activity (10 Years)

Years Active: 1999-2021
Publications (10 Years): 2

Top Topics

Programmable Logic Controller

Data Transmission

Image Filtering

Top Venues

Turkish J. Electr. Eng. Comput. Sci.

Publications

Latif Akçay, Siddika Berna Örs
Comparison of RISC-V and transport triggered architectures for a postquantum cryptography application. Turkish J. Electr. Eng. Comput. Sci. 29 (1) (2021)
Elif Nur Isman, Canberk Topal, Latif Akçay, Siddika Berna Örs
Instruction Extension of an Open Source RV32IMC Core for NTRU Cryptosystem. ECCTD (2020)
Burcu Akmansayar, Salman Kurtulan, Siddika Berna Örs
Design of core blocks and implementation on a programmable logic controller for a train signalization system. SIU (2015)
Mehmet Akif Ozkan, Siddika Berna Örs
Data transmission via GSM voice channel for end to end security. ICCE-Berlin (2015)
Ahmet Dogan, Siddika Berna Örs, Gökay Saldamli
Analyzing and comparing the AES architectures for their power consumption. J. Intell. Manuf. 25 (2) (2014)
Ahmet Cagri Bagbaba, Siddika Berna Örs, Ahmet Turan Erozan
Image filtering processor and its applications. SIU (2014)
Subutay Giray Baskir, Siddika Berna Örs
Implementation of a secure RFID protocol. SIU (2013)
Ahmet Turan Erozan, Subutay Giray Baskir, Siddika Berna Örs
Hardware/Software codesign for watermarking in DCT domain. SIU (2013)
Ahmet Aris, Siddika Berna Örs, Gökay Saldamli
Architectures for Fast Modular Multiplication. DSD (2011)
Mehmet Soybali, Siddika Berna Örs, Gökay Saldamli
Implementation of a PUF Circuit on a FPGA. NTMS (2011)
Keklik Alptekin Bayam, Siddika Berna Örs
Differential Power Analysis resistant hardware implementation of the RSA cryptosystem. ISCAS (2008)
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, Siddika Berna Örs
Low-cost implementations of NTRU for pervasive security. ASAP (2008)
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier. Int. J. Embed. Syst. 3 (4) (2008)
Levent Ordu, Siddika Berna Örs
Power Analysis Resistant Hardware Implementations of AES. ICECS (2007)
Elke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede
Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems. Comput. Electr. Eng. 33 (5-6) (2007)
François-Xavier Standaert, Siddika Berna Örs, Bart Preneel
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? CHES (2004)
Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
An FPGA Implementation of a Montgomery Multiplier Over GF(2^m). Comput. Artif. Intell. 23 (5) (2004)
Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel
Power-Analysis Attack on an ASIC AES implementation. ITCC (2) (2004)
Nele Mentens, Siddika Berna Örs, Bart Preneel
). ACM Great Lakes Symposium on VLSI (2004)
François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel
Power Analysis Attacks Against FPGA Implementations of the DES. FPL (2004)
Lejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs
Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems. CT-RSA (2004)
Lejla Batina, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
Hardware architectures for public key cryptography. Integr. 34 (1-2) (2003)
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
Hardware Implementation of an Elliptic Curve Processor over GF(p). ASAP (2003)
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array. IPDPS (2003)
Siddika Berna Örs, Elisabeth Oswald, Bart Preneel
Power-Analysis Attacks on an FPGA - First Experimental Results. CHES (2003)
Siddika Berna Örs, Ahmet Dervisoglu
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. EUROMICRO (1999)