Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array.
Siddika Berna ÖrsLejla BatinaBart PreneelJoos VandewallePublished in: IPDPS (2003)
Keyphrases
- hardware implementation
- systolic array
- parallel architecture
- fpga implementation
- reconfigurable architecture
- xilinx virtex
- signal processing
- efficient implementation
- low end
- field programmable gate array
- smart card
- data flow
- dedicated hardware
- hardware design
- image processing algorithms
- memory management
- software implementation
- integer arithmetic
- pipeline architecture
- neural network
- floating point
- public key cryptosystems
- general purpose processors
- feature extraction