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Siddhartha Joshi
ORCID
Publication Activity (10 Years)
Years Active: 2015-2020
Publications (10 Years): 6
Top Topics
Low Power
Logic Circuits
Alpha Beta
Content Addressable Memory
Top Venues
IEEE Trans. Very Large Scale Integr. Syst.
ICCD
Sensors
MWSCAS
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Publications
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Brett Shook
,
Prateek Bhansali
,
Chandramouli V. Kashyap
,
Chirayu Amin
,
Siddhartha Joshi
MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design.
DAC
(2020)
Farah Fahim
,
Siddhartha Joshi
,
Seda Ogrenci Memik
,
Hooman Mohseni
A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree.
IEEE Trans. Very Large Scale Integr. Syst.
28 (2) (2020)
Farah Fahim
,
Simone Bianconi
,
Jacob Rabinowitz
,
Siddhartha Joshi
,
Hooman Mohseni
Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems.
Sensors
20 (9) (2020)
Dawei Li
,
Siddhartha Joshi
,
Ji-Hoon Kim
,
Seda Ogrenci Memik
End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
25 (9) (2017)
Siddhartha Joshi
,
Dawei Li
,
Seda Ogrenci Memik
,
Grzegorz Deptuch
,
James Hoff
,
Sergo Jindariani
,
Tiehui Liu
,
Jamieson Olsen
,
Nhan Tran
A content addressable memory with multi-Vdd scheme for low power tunable operation.
MWSCAS
(2017)
Dawei Li
,
Siddhartha Joshi
,
Seda Ogrenci Memik
,
James Hoff
,
Sergo Jindariani
,
Tiehui Liu
,
Jamieson Olsen
,
Nhan Tran
A methodology for power characterization of associative memories.
ICCD
(2015)