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A content addressable memory with multi-Vdd scheme for low power tunable operation.
Siddhartha Joshi
Dawei Li
Seda Ogrenci Memik
Grzegorz Deptuch
James Hoff
Sergo Jindariani
Tiehui Liu
Jamieson Olsen
Nhan Tran
Published in:
MWSCAS (2017)
Keyphrases
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low power
high speed
power consumption
low cost
content addressable memory
single chip
logic circuits
cmos technology
vlsi circuits
real time
low power consumption
image sensor
gate array
vlsi architecture
computer systems
energy efficiency
power reduction
image compression