Sheldon B. Akers Jr.

Publication Activity (10 Years)

Years Active: 1955-1990
Publications (10 Years): 0

Publications

Sheldon B. Akers Jr., Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan
Why is less information from logic simulation more useful in fault simulation? ITC (1990)
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
Test counting: a tool for VLSI testing. IEEE Des. Test 6 (5) (1989)
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
A Group-Theoretic Model for Symmetric Interconnection Networks. IEEE Trans. Computers 38 (4) (1989)
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy, Dov Harel
The Star Graph: An Attractive Alternative to the n-Cube. ICPP (1987)
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
On Group Graphs and Their Fault Tolerance. IEEE Trans. Computers 36 (7) (1987)
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
: A Group Theoretic Model for Symmetric Interconnection Networks. ICPP (1986)
Balakrishnan Krishnamurthy, Sheldon B. Akers Jr.
On the Complexity of Estimating the Size of a Test Set. IEEE Trans. Computers 33 (8) (1984)
Sheldon B. Akers Jr.
On the use of the linear assignment algorithm in module placement. DAC (1981)
Sheldon B. Akers Jr.
Test Generation Techniques. Computer 13 (3) (1980)
Sheldon B. Akers Jr.
Binary Decision Diagrams. IEEE Trans. Computers 27 (6) (1978)
Sheldon B. Akers Jr.
A Logic System for Fault Test Generation. IEEE Trans. Computers 25 (6) (1976)
Sheldon B. Akers Jr.
Fault Diagnosis as a Graph Coloring Problem. IEEE Trans. Computers 23 (7) (1974)
Sheldon B. Akers Jr.
Universal Test Sets for Logic Networks. IEEE Trans. Computers 22 (9) (1973)
Sheldon B. Akers Jr.
Universal Test Sets for Logic Networks SWAT (1972)
Sheldon B. Akers Jr.
A Rectangular Logic Array. IEEE Trans. Computers 21 (8) (1972)
Sheldon B. Akers Jr.
A Rectangular Logic Array SWAT (1971)
Sheldon B. Akers Jr.
R70-40 Module Clustering to Minimize Delay in Digital Networks. IEEE Trans. Computers 19 (10) (1970)
Sheldon B. Akers Jr., James M. Geyer, Donald L. Roberts
IC mask layout with a single conductor layer. DAC (1970)
Sheldon B. Akers Jr.
On Maximum Inversion with Minimum Inverters. IEEE Trans. Computers 17 (2) (1968)
Sheldon B. Akers Jr.
On the Construction of (d, k) Graphs. IEEE Trans. Electron. Comput. 14 (3) (1965)
Sheldon B. Akers Jr.
A Diagrammatic Approach to Multilevel Logic Synthesis. IEEE Trans. Electron. Comput. 14 (2) (1965)
Sheldon B. Akers Jr.
A diagrammatic approach to multi-level logic synthesis SWCT (1964)
Sheldon B. Akers Jr.
Synthesis of combinational logic using three-input majority gates SWCT (1962)
Sheldon B. Akers Jr.
Threshold logic and two-person, zero-sum games SWCT (1961)
Sheldon B. Akers Jr.
A Truth Table Method for the Synthesis of Combinational Logic. IRE Trans. Electron. Comput. 10 (4) (1961)
Sheldon B. Akers Jr., Joyce Friedman
A Non-Numerical Approach to Production Scheduling Problems. Oper. Res. 3 (4) (1955)