Sheayun Lee

Publication Activity (10 Years)

Years Active: 1998-2022
Publications (10 Years): 4

Top Topics

Garbage Collection

Provably Correct

Top Venues

ACM Trans. Embed. Comput. Syst.

ACM Trans. Storage

Publications

Inkyung Kim, Daehee Kim, Sunyoung Kwon, Sheayun Lee, Jaekoo Lee
Fall Detection using Biometric Information Based on Multi-Horizon Forecasting. ICPR (2022)
Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min
FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs. DAC (2018)
Jin-yong Choi, Eyee Hyun Nam, Yoon Jae Seong, Jinhyuk Yoon, Sookwan Lee, Hongseok Kim, Jeongsu Park, Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min
HIL: A Framework for Compositional FTL Development and Provably-Correct Crash Recovery. ACM Trans. Storage 14 (4) (2018)
Hongseok Kim, Eyee Hyun Nam, JiHyuck Yun, Sheayun Lee, Sang Lyul Min
P-BMS: A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Sheayun Lee, Insik Shin, Woonseok Kim, Insup Lee, Sang Lyul Min
A design framework for real-time embedded systems with code size and energy constraints. ACM Trans. Embed. Comput. Syst. 7 (2) (2008)
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
Selective code transformation for dual instruction set processors. ACM Trans. Embed. Comput. Syst. 6 (2) (2007)
Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. CODES+ISSS (2006)
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. SCOPES (2004)
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. WCET (2003)
Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. SCOPES (2003)
Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. LCTES/OM (2001)
Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. OM@PLDI (2001)
Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee
Cache-Conscious Limited Preemptive Scheduling. Real Time Syst. 17 (2-3) (1999)
Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems. LCTES (1998)