Sanjay Vidhyadharan

Publication Activity (10 Years)

Years Active: 2019-2022
Publications (10 Years): 9

Top Topics

Cmos Technology

Top Venues

Microelectron. J.

Circuits Syst. Signal Process.

Wirel. Pers. Commun.

Publications

Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa, Sanjay Vidhyadharan
High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. Circuits Syst. Signal Process. 41 (8) (2022)
Abhay S. Vidhyadharan, Sanjay Vidhyadharan
CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications. Wirel. Pers. Commun. 123 (1) (2022)
Abhay S. Vidhyadharan, Sanjay Vidhyadharan
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM. Microelectron. J. 111 (2021)
Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan
Ternary Half Adder. Circuits Syst. Signal Process. 40 (8) (2021)
Abhay S. Vidhyadharan, Sanjay Vidhyadharan
ternary dynamic Half Adder. Microelectron. J. 107 (2021)
Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, Simhadri Hariprasad
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger. Microelectron. J. 104 (2020)
Sanjay Vidhyadharan, Surya Shankar Dan, Abhay S. Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC. Integr. 73 (2020)
Sanjay Vidhyadharan, Ramakant Ramakant, Abhay S. Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Surya Shankar Dan
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. VLSI Design (2019)
Ramakant Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary, Surya Shankar Dan
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications. VLSI Design (2019)