Robert Schöne

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 27

Top Venues

CoRR

Comput. Sci. Res. Dev.

CLUSTER

ICPE

Dresden University of Technology, Germany (PHD)

Education History

Dresden University of Technology, Germany

PHD

Publications

Robert Schöne, Markus Velten, Daniel Hackenberg, Thomas Ilsche
Energy Efficiency Features of the Intel Alder Lake Architecture. ICPE (2024)
Jonas H. Müller Korndörfer, Ahmed Eleliemy, Osman Seckin Simsek, Thomas Ilsche, Robert Schöne, Florina M. Ciorba
How Do OS and Application Schedulers Interact? An Investigation with Multithreaded Applications. Euro-Par (2023)
Markus Velten, Robert Schöne, Thomas Ilsche, Daniel Hackenberg
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. CoRR (2022)
Markus Velten, Robert Schöne, Thomas Ilsche, Daniel Hackenberg
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. ICPE (2022)
Robert Schöne, Markus Schmidl, Mario Bielert, Daniel Hackenberg
FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests. CoRR (2021)
Robert Schöne, Markus Schmidl, Mario Bielert, Daniel Hackenberg
FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests. CLUSTER (2021)
Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CLUSTER (2021)
Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CoRR (2021)
Christian von Elm, Thomas Ilsche, Robert Schöne, Mario Bielert, Markus Schmidl
Investigating the Cause and Effect of an AMD Zen Energy Management Anomaly. ICPE (Companion) (2021)
Andreas Gocht, Alexander Grund, Robert Schöne
Controlling the Runtime Overhead of Python Monitoring with Selective Instrumentation. ProTools@SC (2021)
Andreas Gocht, Robert Schöne, Jan Frenzel
Advanced Python Performance Monitoring with Score-P. CoRR (2020)
Thomas Ilsche, Daniel Hackenberg, Robert Schöne, Mario Höpfner, Wolfgang E. Nagel
MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data. DAAC@SC (2019)
Andreas Gocht, Christoph Lehmann, Robert Schöne
A New Approach for Automated Feature Selection. GI-Jahrestagung (2019)
Thomas Ilsche, Robert Schöne, Joseph Schuchart, Daniel Hackenberg, Marc Simon, Yiannis Georgiou, Wolfgang E. Nagel
Power measurement techniques for energy-efficient computing: reconciling scalability, resolution, and accuracy. SICS Softw.-Intensive Cyber Phys. Syst. 34 (1) (2019)
Andreas Gocht, Robert Schöne, Mario Bielert
Q-Learning Inspired Self-Tuning for Energy Efficiency in HPC. CoRR (2019)
Andreas Gocht, Robert Schöne, Mario Bielert
Q-Learning Inspired Self-Tuning for Energy Efficiency in HPC. HPCS (2019)
Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht, Daniel Hackenberg
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. CoRR (2019)
Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht, Daniel Hackenberg
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. HPCS (2019)
Thomas Ilsche, Robert Schöne, Philipp Joram, Mario Bielert, Andreas Gocht
System Monitoring with lo2s: Power and Runtime Impact of C-State Transitions. IPDPS Workshops (2018)
Andreas Gocht, Christoph Lehmann, Robert Schöne
A New Approach for Automated Feature Selection. IEEE BigData (2018)
Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson
The Shift from Processor Power Consumption to Performance Variations: Fundamental Implications at Scale. CoRR (2018)
Thomas Ilsche, Robert Schöne, Mario Bielert, Andreas Gocht, Daniel Hackenberg
lo2s - Multi-core System and Application Performance Analysis for Linux. CLUSTER (2017)
Daniel Molka, Robert Schöne, Daniel Hackenberg, Wolfgang E. Nagel
Detecting Memory-Boundedness with Hardware Performance Counters. ICPE (2017)
Thomas Ilsche, Marcus Hähnel, Robert Schöne, Mario Bielert, Daniel Hackenberg
Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-core Systems. Euro-Par Workshops (2017)
Mohammed Sourouri, Espen Birger Raknes, Nico Reissmann, Johannes Langguth, Daniel Hackenberg, Robert Schöne, Per Gunnar Kjeldsberg
Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures. SC (2017)
Robert Schöne, Thomas Ilsche, Mario Bielert, Daniel Molka, Daniel Hackenberg
Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors. E2SC@SC (2016)
Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson
The shift from processor power consumption to performance variations: fundamental implications at scale. Comput. Sci. Res. Dev. 31 (4) (2016)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Wolfgang E. Nagel
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture. ICPP (2015)
Robert Schöne, Daniel Molka, Michael Werner
Wake-up latencies for processor idle states on current x86 processors. Comput. Sci. Res. Dev. 30 (2) (2015)
Thomas Ilsche, Daniel Hackenberg, Stefan Graul, Robert Schöne, Joseph Schuchart
Power measurements for compute nodes: Improving sampling rates, granularity and accuracy. IGSC (2015)
Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Daniel Molka, Joseph Schuchart, Robin Geyer
An Energy Efficiency Feature Survey of the Intel Haswell Processor. IPDPS Workshops (2015)
Robert Schöne, Daniel Molka
Integrating performance analysis and energy efficiency optimizations in a unified environment. Comput. Sci. Res. Dev. 29 (3-4) (2014)
Robert Schöne, Jan Treibig, Manuel F. Dolz, Carla Guillén, Carmen B. Navarrete, Michael Knobloch, Barry Rountree
Tools and methods for measuring and tuning the energy efficiency of HPC systems. Sci. Program. 22 (4) (2014)
Daniel Molka, Daniel Hackenberg, Robert Schöne
Main memory and cache performance of intel sandy bridge and AMD bulldozer. MSPC@PLDI (2014)
Florina M. Ciorba, Thomas Ilsche, Elke Franz, Stefan Pfennig, Christian Scheunert, Ulf Markwardt, Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Andreas Knüpfer, Wolfgang E. Nagel, Eduard A. Jorswieck, Matthias S. Müller
Analysis of Parallel Applications on a High Performance-Low Energy Computer. Euro-Par Workshops (2) (2014)
Daniel Hackenberg, Thomas Ilsche, Joseph Schuchart, Robert Schöne, Wolfgang E. Nagel, Marc Simon, Yiannis Georgiou
HDEEM: high definition energy efficiency monitoring. E2SC@SC (2014)
Robert Schöne, Andreas Knüpfer, Daniel Molka
Potentials and Limitations for Energy Efficiency Auto-Tuning. PARCO (2013)
Daniel Hackenberg, Roland Oldenburg, Daniel Molka, Robert Schöne
Introducing FIRESTARTER: A processor stress test utility. IGCC (2013)
Daniel Hackenberg, Thomas Ilsche, Robert Schöne, Daniel Molka, Maik Schmidt, Wolfgang E. Nagel
Power measurement techniques on standard compute nodes: A quantitative comparison. ISPASS (2013)
Robert Schöne, Daniel Hackenberg, Daniel Molka
Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors. HotPower (2012)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Timo Minartz, Wolfgang E. Nagel
Flexible workload generation for HPC cluster efficiency benchmarking. Comput. Sci. Res. Dev. 27 (4) (2012)
Robert Schöne, Daniel Hackenberg, Daniel Molka
Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation. HotPower@SOSP (2011)
Robert Schöne, Daniel Hackenberg
On-line analysis of hardware performance events for workload characterization and processor frequency scaling decisions. ICPE (2011)
Daniel Molka, Robert Schöne, Daniel Hackenberg, Matthias S. Müller
Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86_64 Systems. ICA3PP (1) (2011)
Robert Schöne, Ronny Tschüter, Thomas Ilsche, Daniel Hackenberg
The VampirTrace Plugin Counter Interface: Introduction and Examples. Euro-Par Workshops (2010)
Daniel Hackenberg, Robert Schöne, Daniel Molka, Matthias S. Müller, Andreas Knüpfer
Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks. Comput. Sci. Res. Dev. 25 (3-4) (2010)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller
Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. Green Computing Conference (2010)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. PACT (2009)
Katharina Rasch, Robert Schöne, Vitaliy Ostropytskyy, Hartmut Mix, Mathilde Romberg
The Chemomentum Data Services - A Flexible Solution for Data Handling in UNICORE. Euro-Par Workshops (2008)
Robert Schöne, Wolfgang E. Nagel, Stefan Pflüger
Analyzing Cache Bandwidth on the Intel Core 2 Architecture. PARCO (2007)
Daniel Hackenberg, Robert Schöne, Wolfgang E. Nagel, Stefan Pflüger
Optimizing OpenMP Parallelized DGEMM Calls on SGI Altix 3700. Euro-Par (2006)
Robert Schöne, Guido Juckeland, Wolfgang E. Nagel, Stefan Pflüger, R. Wloch
Performance Comparison and Optimization: Case Studies using BenchIT. PARCO (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Robert Schöne