Daniel Hackenberg

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 19

Top Topics

Energy Efficiency

Energy Management

Code Generation

Top Venues

Publications

Robert Schöne, Markus Velten, Daniel Hackenberg, Thomas Ilsche
Energy Efficiency Features of the Intel Alder Lake Architecture. ICPE (2024)
Markus Velten, Robert Schöne, Thomas Ilsche, Daniel Hackenberg
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. CoRR (2022)
Markus Velten, Robert Schöne, Thomas Ilsche, Daniel Hackenberg
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. ICPE (2022)
Robert Schöne, Markus Schmidl, Mario Bielert, Daniel Hackenberg
FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests. CoRR (2021)
Robert Schöne, Markus Schmidl, Mario Bielert, Daniel Hackenberg
FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests. CLUSTER (2021)
Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CLUSTER (2021)
Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CoRR (2021)
Thomas Ilsche, Daniel Hackenberg, Robert Schöne, Mario Höpfner, Wolfgang E. Nagel
MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data. DAAC@SC (2019)
Thomas Ilsche, Robert Schöne, Joseph Schuchart, Daniel Hackenberg, Marc Simon, Yiannis Georgiou, Wolfgang E. Nagel
Power measurement techniques for energy-efficient computing: reconciling scalability, resolution, and accuracy. SICS Softw.-Intensive Cyber Phys. Syst. 34 (1) (2019)
Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht, Daniel Hackenberg
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. CoRR (2019)
Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht, Daniel Hackenberg
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. HPCS (2019)
Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson
The Shift from Processor Power Consumption to Performance Variations: Fundamental Implications at Scale. CoRR (2018)
Joseph Schuchart, Michael Gerndt, Per Gunnar Kjeldsberg, Michael Lysaght, David Horák, Lubomír Ríha, Andreas Gocht, Mohammed Sourouri, Madhura Kumaraswamy, Anamika Chowdhury, Magnus Jahre, Kai Diethelm, Othman Bouizi, Umbreen Sabir Mian, Jakub Kruzík, Radim Sojka, Martin Beseda, Venkatesh Kannan, Zakaria Bendifallah, Daniel Hackenberg, Wolfgang E. Nagel
The READEX formalism for automatic tuning for energy efficiency. Computing 99 (8) (2017)
Thomas Ilsche, Robert Schöne, Mario Bielert, Andreas Gocht, Daniel Hackenberg
lo2s - Multi-core System and Application Performance Analysis for Linux. CLUSTER (2017)
Daniel Molka, Robert Schöne, Daniel Hackenberg, Wolfgang E. Nagel
Detecting Memory-Boundedness with Hardware Performance Counters. ICPE (2017)
Thomas Ilsche, Marcus Hähnel, Robert Schöne, Mario Bielert, Daniel Hackenberg
Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-core Systems. Euro-Par Workshops (2017)
Mohammed Sourouri, Espen Birger Raknes, Nico Reissmann, Johannes Langguth, Daniel Hackenberg, Robert Schöne, Per Gunnar Kjeldsberg
Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures. SC (2017)
Robert Schöne, Thomas Ilsche, Mario Bielert, Daniel Molka, Daniel Hackenberg
Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors. E2SC@SC (2016)
Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson
The shift from processor power consumption to performance variations: fundamental implications at scale. Comput. Sci. Res. Dev. 31 (4) (2016)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Wolfgang E. Nagel
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture. ICPP (2015)
Heiko Gewald, Daniel Hackenberg, Andy Weeger
Business Strategy, IT Management and Business Value - a tripartite interaction? AMCIS (2015)
Thomas Scogland, Jonathan Azose, David Rohr, Suzanne Rivoire, Natalie J. Bates, Daniel Hackenberg
Node variability in large-scale power measurements: perspectives from the Green500, Top500 and EEHPCWG. SC (2015)
Thomas Ilsche, Daniel Hackenberg, Stefan Graul, Robert Schöne, Joseph Schuchart
Power measurements for compute nodes: Improving sampling rates, granularity and accuracy. IGSC (2015)
Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Daniel Molka, Joseph Schuchart, Robin Geyer
An Energy Efficiency Feature Survey of the Intel Haswell Processor. IPDPS Workshops (2015)
Daniel Molka, Daniel Hackenberg, Robert Schöne
Main memory and cache performance of intel sandy bridge and AMD bulldozer. MSPC@PLDI (2014)
Florina M. Ciorba, Thomas Ilsche, Elke Franz, Stefan Pfennig, Christian Scheunert, Ulf Markwardt, Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Andreas Knüpfer, Wolfgang E. Nagel, Eduard A. Jorswieck, Matthias S. Müller
Analysis of Parallel Applications on a High Performance-Low Energy Computer. Euro-Par Workshops (2) (2014)
Daniel Hackenberg, Thomas Ilsche, Joseph Schuchart, Robert Schöne, Wolfgang E. Nagel, Marc Simon, Yiannis Georgiou
HDEEM: high definition energy efficiency monitoring. E2SC@SC (2014)
Daniel Hackenberg, Roland Oldenburg, Daniel Molka, Robert Schöne
Introducing FIRESTARTER: A processor stress test utility. IGCC (2013)
Daniel Hackenberg, Thomas Ilsche, Robert Schöne, Daniel Molka, Maik Schmidt, Wolfgang E. Nagel
Power measurement techniques on standard compute nodes: A quantitative comparison. ISPASS (2013)
Robert Schöne, Daniel Hackenberg, Daniel Molka
Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors. HotPower (2012)
Matthias S. Müller, John Baron, William C. Brantley, Huiyu Feng, Daniel Hackenberg, Robert Henschel, Gabriele Jost, Daniel Molka, Chris Parrott, Joe Robichaux, Pavel Shelepugin, G. Matthijs van Waveren, Brian Whitney, Kalyan Kumaran
SPEC OMP2012 - An Application Benchmark Suite for Parallel Systems Using OpenMP. IWOMP (2012)
Daniel Hackenberg, Guido Juckeland, Holger Brunst
Performance analysis of multi-level parallelism: inter-node, intra-node and hardware accelerators. Concurr. Comput. Pract. Exp. 24 (1) (2012)
Michael Kluge, Daniel Hackenberg, Wolfgang E. Nagel
Collecting Distributed Performance Data with Dataheap: Generating and Exploiting a Holistic System View. ICCS (2012)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Timo Minartz, Wolfgang E. Nagel
Flexible workload generation for HPC cluster efficiency benchmarking. Comput. Sci. Res. Dev. 27 (4) (2012)
Robert Schöne, Daniel Hackenberg, Daniel Molka
Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation. HotPower@SOSP (2011)
Robert Schöne, Daniel Hackenberg
On-line analysis of hardware performance events for workload characterization and processor frequency scaling decisions. ICPE (2011)
Daniel Molka, Robert Schöne, Daniel Hackenberg, Matthias S. Müller
Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86_64 Systems. ICA3PP (1) (2011)
Robert Schöne, Ronny Tschüter, Thomas Ilsche, Daniel Hackenberg
The VampirTrace Plugin Counter Interface: Introduction and Examples. Euro-Par Workshops (2010)
Daniel Hackenberg, Robert Schöne, Daniel Molka, Matthias S. Müller, Andreas Knüpfer
Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks. Comput. Sci. Res. Dev. 25 (3-4) (2010)
Daniel Hackenberg, Guido Juckeland, Holger Brunst
High Resolution Program Flow Visualization of Hardware Accelerated Hybrid Multi-core Applications. CCGRID (2010)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller
Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. Green Computing Conference (2010)
Holger Brunst, Daniel Hackenberg, Guido Juckeland, Heide Rohling
Comprehensive Performance Tracking with Vampir 7. Parallel Tools Workshop (2009)
Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. MICRO (2009)
Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. PACT (2009)
Daniel Hackenberg, Holger Brunst, Wolfgang E. Nagel
Event Tracing and Visualization for Cell Broadband Engine Systems. Euro-Par (2008)
Daniel Hackenberg, Robert Schöne, Wolfgang E. Nagel, Stefan Pflüger
Optimizing OpenMP Parallelized DGEMM Calls on SGI Altix 3700. Euro-Par (2006)