Reza Hashemian

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 17

Top Topics

Square Matrices

Analog Circuits

Transfer Function

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Reza Hashemian
Extended "A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits". IEEE Trans. Circuits Syst. II Express Briefs 71 (2) (2024)
Reza Hashemian
Quick Access to Circuit Transfer Functions via NAM Determinant/Cofactors Using UaL Technique. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Reza Hashemian
A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Reza Hashemian
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method. ISCAS (2021)
Reza Hashemian
Constructing Circuit Transfer Functions directly from the State Equations, Using Convolutions. EIT (2020)
Reza Hashemian
s-Expanded Transfer Function using UaL Decomposition with Convolution & Deconvolution. ISCAS (2020)
Reza Hashemian
UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices. IEEE Trans. Circuits Syst. II Express Briefs (4) (2020)
Reza Hashemian
Design of Analog Circuits for Continuously Changing Constraints Using Fixator Norator Pairs. MWSCAS (2019)
Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian
Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits. J. Circuits Syst. Comput. 27 (3) (2018)
Reza Hashemian
Amplifier Design for Specified Frequency Response Profiles Using Nullors-Hearing Aids, a Case Study. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian
A nullor approach to the design of analog circuits for a desirable performance. Microelectron. J. 78 (2018)
Reza Hashemian
A Comprehensive Nodal/Branch Circuit Analysis Including Fixator-Norator Pairs in Analog Circuits. MWSCAS (2018)
Reza Hashemian, Mounika Vanga, Mahmoud Rahat
Identifying and 3D Displaying Poles and Zeros in Analog Circuit Transfer Functions: Bode Surfaces. Circuits Syst. Signal Process. 36 (6) (2017)
Reza Hashemian
Nullors in amplifier design for bandwidth using multiple feedbacks. CCECE (2017)
Reza Hashemian
RC and RL to LC circuit conversion, and its application in poles and zeros identification. ICECS (2016)
Reza Hashemian
Finding poles and zeros in an analog circuit directly from its conductance matrix using eigenvalues. Comput. Electr. Eng. 56 (2016)
Reza Hashemian
Application of nullors in designing analog circuits for bandwidth. EIT (2016)
Reza Hashemian
S-plane bode plots - identifying poles and zeros in a circuit transfer function. LASCAS (2015)
Reza Hashemian
Identification and extraction of all real axis poles and zeros in RC and RL circuits. EIT (2015)
Reza Hashemian
Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Reza Hashemian
Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Kamran Ravanasa, Reza Hashemian
vLab, a high speed multi-accesses parallel processing remote laboratory access for FPGA design technology. EIT (2014)
Reza Hashemian
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20 (12) (2012)
Reza Hashemian
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs. VLSI Design 2010 (2010)
Reza Hashemian
Use of local biasing in designing analog integrated circuits. EIT (2008)
Reza Hashemian, Jason Riddley
FPGA e-Lab, a Technique to Remote Access a Laboratory to Design and Test. MSE (2007)
Reza Hashemian
Designing Analog Circuits with Reduced Biasing Power. ICECS (2006)
Reza Hashemian
Condensed table of Huffman coding, a new approach to efficient decoding. IEEE Trans. Commun. 52 (1) (2004)
Reza Hashemian, Bipin Sreedharan
A Hybrid Number System And Its Application In FPGA-DSP Technology. ITCC (2) (2004)
Reza Hashemian
Direct Huffman Coding And Decoding Using The Table Of Code-Lengths. ITCC (2003)
Reza Hashemian
Memory efficient and high-speed search Huffman coding. IEEE Trans. Commun. 43 (10) (1995)
Reza Hashemian
Design of a 54-bit adder using a modified Manchester carry chain. Great Lakes Symposium on VLSI (1994)
Reza Hashemian
High speed search and memory efficient Huffman coding. ISCAS (1993)
Reza Hashemian
An alternative algorithm for high speed multiplication and addition using growing technique. Great Lakes Symposium on VLSI (1992)
Reza Hashemian
Parallel Addition Using Pipeline Structure. ICPP (1) (1990)
Reza Hashemian
Square Rooting Algorithms for Integer and Floatingg-Point Numbers. IEEE Trans. Computers 39 (8) (1990)