Prashanth H. C.

Publication Activity (10 Years)

Years Active: 2022-2024
Publications (10 Years): 23

Top Topics

Exact And Approximate

Parallel Hardware

Top Venues

ACM Great Lakes Symposium on VLSI

EURASIP J. Audio Speech Music. Process.

Publications

Bindu G. Gowda, Prashanth H. C., V. N. Muralidhara, Madhav Rao
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach. ISQED (2024)
Prashanth H. C., Madhav Rao
Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems. ISQED (2024)
Prashanth H. C., Madhav Rao
Performance Analysis of OFA-NAS ResNet Topologies Across Diverse Hardware Compute Units. ACM Great Lakes Symposium on VLSI (2024)
Prashanth H. C., Yash Dharmesh Mogal, Madhav Rao
Design-Space Exploration of Systolic Array for Edge Inferencing Applications. AIMLSystems (2023)
S. N. Raghava, Prashanth H. C., Bindu G. Gowda, Pratyush Nandi, Madhav Rao
Design-Space Exploration of Multiplier Approximation in CNNs. ISVLSI (2023)
Mayank Kabra, Shreyas V. S, Prashanth H. C., Kedar Deshpande, Madhav Rao
GCells: A Graph-Search Approach to Design Custom Cells for Computational Subsystems. DSD (2023)
Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao
eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application. ISQED (2023)
Prashanth H. C., Madhav Rao
Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. IJCCI (2023)
Prashanth H. C., Sriniketh S. S, Shrikrishna Hebbar, Chinmaye R, Madhav Rao
SQRTLIB : Library of Hardware Square Root Designs. ISQED (2023)
Bindu G. Gowda, Prashanth H. C., Madhav Rao
IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit. ACM Great Lakes Symposium on VLSI (2023)
Prashanth H. C., Madhav Rao, Dhanya Eledath, V. Ramasubramanian
Correction: Trainable windows for SincNet architecture. EURASIP J. Audio Speech Music. Process. 2023 (1) (2023)
Harshita Gupta, Mayank Kabra, Nitin D. Patwari, Prashanth H. C., Madhav Rao
Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA. ISQED (2023)
Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao
HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD. ISQED (2023)
Sai Karthik Nandigama, Prashanth H. C., Madhav Rao
Design and Evaluation of Inexact Computation based Systolic Array for Convolution. LASCAS (2023)
Sai Karthik Nandigama, Bindu G. Gowda, Prashanth H. C., Madhav Rao
EBASA: Error Balanced Approximate Systolic Array Architecture Design. ACM Great Lakes Symposium on VLSI (2023)
Bindu G. Gowda, Prashanth H. C., Madhav Rao
Error Diluted Approximate Multipliers Using Positive And Negative Compressors. ISQED (2023)
Prashanth H. C., Prashanth Jonna, Madhav Rao
CellFlow: Automated Standard Cell Design Flow. ISVLSI (2023)
Prashanth H. C., Madhav Rao, Dhanya Eledath, Ramasubramanian C
Trainable windows for SincNet architecture. EURASIP J. Audio Speech Music. Process. 2023 (1) (2023)
Prashanth H. C., Soujanya S. R, Bindu G. Gowda, Madhav Rao
Design and Evaluation of In-Exact Compressor based Approximate Multipliers. ACM Great Lakes Symposium on VLSI (2022)
Mayank Kabra, Prashanth H. C., Madhav Rao
Design and Evaluation of Performance-efficient SoC-on-FPGA for Cloud-based Healthcare Applications. NorCAS (2022)
Prashanth H. C., Madhav Rao
SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators. ICCD (2022)
Prashanth H. C., Madhav Rao
Evolutionary Standard Cell Synthesis of Unconventional Designs. ACM Great Lakes Symposium on VLSI (2022)
Prashanth H. C., Madhav Rao
Improving Digital Circuit Synthesis of Complex Functions using Binary Weighted Fitness and Variable Mutation Rate in Cartesian Genetic Programming. IJCCI (2022)