Parth Parekh

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 16

Top Topics

Semantic Parser

Unsupervised Anomaly Detection

Signal Processing

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Microelectron. J.

Publications

Parth Parekh, Cedric McGuire, Jake Imyak
Underwater Robotics Semantic Parser Assistant. CoRR (2023)
Fei Yuan, Parth Parekh, Yushi Zhou
Bi-Directional Gated Ring Oscillator Time Integrator. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Parth Parekh, Fei Yuan, Yushi Zhou
Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. Microelectron. J. 119 (2022)
Parth Parekh, Fei Yuan, Yushi Zhou
Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing. MWSCAS (2022)
Parth Parekh, Fei Yuan, Yushi Zhou
Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Parth Parekh, Fei Yuan, Yushi Zhou
All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing. NEWCAS (2022)
Parth Parekh, Fei Yuan, Yushi Zhou
Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. MWSCAS (2021)
Parth Parekh, Fei Yuan, Yushi Zhou
Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability. MWSCAS (2020)
Fei Yuan, Parth Parekh
Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator. IET Circuits Devices Syst. 14 (1) (2020)
Parth Parekh, Fei Yuan, Yushi Zhou
All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. MWSCAS (2020)
Fei Yuan, Parth Parekh
Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Fei Yuan, Parth Parekh
Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration. MWSCAS (2019)
Fei Yuan, Parth Parekh
All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator. MWSCAS (2019)
Young Jun Park, Parth Parekh, Fei Yuan
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. Microelectron. J. 81 (2018)
Parth Parekh, Fei Yuan
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. NEWCAS (2018)
Edward Yu, Parth Parekh
A Bayesian Ensemble for Unsupervised Anomaly Detection. CoRR (2016)