Nicola Concer

Publication Activity (10 Years)

Years Active: 2006-2015
Publications (10 Years): 1

Top Venues

DATE

SoCC

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

University of Bologna, Italy (PHD)

Education History

University of Bologna, Italy

PHD

Publications

Sivakumar Thangamuthu, Nicola Concer, Pieter J. L. Cuijpers, Johan J. Lukkien
Analysis of ethernet-switch traffic shapers for in-vehicle networking applications. DATE (2015)
Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni
Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (12) (2013)
Young-Jin Yoon, Nicola Concer, Luca P. Carloni
Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip. SoCC (2012)
Nicola Concer, Andrea Vesco, Riccardo Scopigno, Luca P. Carloni
A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip. ICCD (2011)
Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni
The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (6) (2010)
Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni
Virtual channels vs. multiple physical networks: a comparative analysis. DAC (2010)
Nicola Concer, Salvatore Iamundo, Luciano Bononi
aEqualized: A novel routing algorithm for the Spidergon Network On Chip. DATE (2009)
Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni
CTC: An end-to-end flow control protocol for multi-core systems-on-chip. NOCS (2009)
Nicola Concer, Michele Petracca, Luca P. Carloni
Distributed flit-buffer flow control for networks-on-chip. CODES+ISSS (2008)
Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli
NoC Topologies Exploration based on Mapping and Simulation Models. DSD (2007)
Luciano Bononi, Nicola Concer
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. DATE Designers' Forum (2006)

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Publication Activity (10 Years)

Top Topics

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Nicola Concer