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Mursina Khatun
Publication Activity (10 Years)
Years Active: 2024-2024
Publications (10 Years): 3
Top Topics
Power Reduction
Low Voltage
Circuit Design
Nm Technology
Top Venues
ISCAS
ISQED
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Publications
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Prema Kumar Govindaswamy
,
Mursina Khatun
,
Vijay Shankar Pasupureddi
-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS.
ISCAS
(2024)
Prema Kumar Govindaswamy
,
Mursina Khatun
,
Vijay Shankar Pasupureddi
A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS.
ISCAS
(2024)
Prema Kumar Govindaswamy
,
Mursina Khatun
,
Vijay Shankar Pasupureddi
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.
ISQED
(2024)