A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS.
Prema Kumar GovindaswamyMursina KhatunVijay Shankar PasupureddiPublished in: ISCAS (2024)
Keyphrases
- energy efficient
- cmos technology
- high speed
- nm technology
- power consumption
- energy efficiency
- wireless sensor networks
- low power
- circuit design
- silicon on insulator
- energy consumption
- metal oxide semiconductor
- sensor networks
- analog vlsi
- low voltage
- topology control
- random access memory
- data dissemination
- power dissipation
- power reduction
- base station
- low cost
- multi core architecture
- multi hop
- delay insensitive
- data gathering
- routing protocol
- power management
- flip flops
- parallel processing
- data sets
- image sensor
- integrated circuit
- response time
- data transmission
- end to end