A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.
Prema Kumar GovindaswamyMursina KhatunVijay Shankar PasupureddiPublished in: ISQED (2024)
Keyphrases
- energy efficient
- nm technology
- power consumption
- energy efficiency
- cmos technology
- high speed
- low power
- silicon on insulator
- circuit design
- energy consumption
- wireless sensor networks
- metal oxide semiconductor
- sensor networks
- analog vlsi
- power dissipation
- low voltage
- topology control
- delay insensitive
- random access memory
- power reduction
- multi hop
- data gathering
- low cost
- flip flops
- base station
- data dissemination
- power management
- multi core architecture
- data transmission
- routing protocol
- response time
- data sets
- integrated circuit
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