Morio Ikesaka

Publication Activity (10 Years)

Years Active: 1985-1993
Publications (10 Years): 0

Publications

Hiroaki Ishihata, Toshiyuki Shimizu, Takeshi Horie, Satoshi Inano, Morio Ikesaka
Architecture of highly parallel ap1000 computer. Systems and Computers in Japan 24 (7) (1993)
Takeshi Horie, Hiroaki Ishihata, Morio Ikesaka
Design and Implementation of an Interconnection Network for the AP1000. IFIP Congress (1) (1992)
Takeshi Horie, Hiroaki Ishihata, Toshiyuki Shimizu, Sadayuki Kato, Satoshi Inano, Morio Ikesaka
AP1000 Architecture and Performance of LU Decomposition. ICPP (1) (1991)
Mitsuo Ishii, Morio Ikesaka, Hiroaki Ishihata
A Highly Parallel Processor CAP. Systems and Computers in Japan 21 (3) (1990)
Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata
Cellular array processor CAP and applications. J. VLSI Signal Process. 1 (1) (1989)
Hiroyuki Sato, Mitsuo Ishii, Keiji Sato, Morio Ikesaka, Hiroaki Ishihata, Masanori Kakimoto, Katsuhiko Hirota, Kouichi Inoue
Fast image generation of construcitve solid geometry using a cellular array processor. SIGGRAPH (1985)