Mandalagiri S. Chandrasekhar

Publication Activity (10 Years)

Years Active: 1982-1997
Publications (10 Years): 0

Publications

Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace
Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits. VLSI Design 5 (2) (1997)
David E. Wallace, Mandalagiri S. Chandrasekhar
High-Level Delay Estimation for Technology-Independent Logic Equations. ICCAD (1990)
Mandalagiri S. Chandrasekhar, Melvin A. Breuer
Optimal routing of two rectangular blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (4) (1989)
Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt
Application of Term Rewriting Techniques to Hardware Design Verification. DAC (1987)
Mandalagiri S. Chandrasekhar, Melvin A. Breuer
Optimum placement of two rectangular blocks. DAC (1982)