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Lok-Won Kim
ORCID
Publication Activity (10 Years)
Years Active: 2002-2023
Publications (10 Years): 7
Top Topics
Security Breaches
Deep Learning
Kernel Parameters
Restricted Boltzmann Machine
Top Venues
IEEE Trans. Reliab.
IEEE Access
ACM Trans. Reconfigurable Technol. Syst.
CoRR
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Publications
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Quang Hieu Vo
,
Linh-Tam Tran
,
Sung-Ho Bae
,
Lok-Won Kim
,
Choong Seon Hong
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree.
ICCV
(2023)
Lok-Won Kim
,
Hieu Quang Vo
,
Choong Seon Hong
Runtime Testability on Autonomous System.
IEEE Trans. Reliab.
72 (1) (2023)
Hieu Quang Vo
,
Linh-Tam Tran
,
Sung-Ho Bae
,
Lok-Won Kim
,
Choong Seon Hong
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree.
CoRR
(2023)
Hieu Quang Vo
,
Sang Hoon Hong
,
Lok-Won Kim
,
Choong Seon Hong
Integrated Optimization in Training Process for Binary Neural Network.
ICOIN
(2023)
Hieu Quang Vo
,
Linh Ngoc Le
,
Faaiz Asim
,
Lok-Won Kim
,
Choong Seon Hong
A Deep Learning Accelerator Based on a Streaming Architecture for Binary Neural Networks.
IEEE Access
10 (2022)
Madyan Alsenwi
,
Ibrar Yaqoob
,
Shashi Raj Pandey
,
Yan Kyaw Tun
,
Anupam Kumar Bairagi
,
Lok-Won Kim
,
Choong Seon Hong
Towards Coexistence of Cellular and WiFi Networks in Unlicensed Spectrum: A Neural Networks Based Approach.
IEEE Access
7 (2019)
Lok-Won Kim
DeepX: Deep Learning Accelerator for Restricted Boltzmann Machine Artificial Neural Networks.
IEEE Trans. Neural Networks Learn. Syst.
29 (5) (2018)
Lok-Won Kim
,
Dong-U Lee
,
John D. Villasenor
Automated Iterative Pipelining for ASIC Design.
ACM Trans. Design Autom. Electr. Syst.
20 (2) (2015)
Lok-Won Kim
,
John D. Villasenor
Dynamic Function Verification for System on Chip Security Against Hardware-Based Attacks.
IEEE Trans. Reliab.
64 (4) (2015)
Jaeyong Chung
,
Lok-Won Kim
Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems.
IEEE Trans. Computers
64 (11) (2015)
Lok-Won Kim
,
Sameh W. Asaad
,
Ralph Linsker
A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network.
ACM Trans. Reconfigurable Technol. Syst.
7 (1) (2014)
Lok-Won Kim
,
John D. Villasenor
Dynamic Function Replacement for System-on-Chip Security in the Presence of Hardware-Based Attacks.
IEEE Trans. Reliab.
63 (2) (2014)
Dong-U Lee
,
Lok-Won Kim
,
John D. Villasenor
Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform.
IEEE Trans. Image Process.
21 (2) (2012)
Lok-Won Kim
,
John D. Villasenor
A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses.
IEEE Trans. Very Large Scale Integr. Syst.
19 (10) (2011)
Woo-Seop Kim
,
Lok-Won Kim
,
Chang-Eun Lee
,
Kyeong-Deok Moon
,
Suki Kim
A control network architecture based on EIA-709.1 protocol for power line data communications.
IEEE Trans. Consumer Electron.
48 (3) (2002)