Laurence E. Turner

Publication Activity (10 Years)

Years Active: 1984-2006
Publications (10 Years): 0

Publications

Dan Cyca, Laurence E. Turner
A C compiler for implementing FPGA based bit-serial DSP systems. FPT (2006)
Dan Cyca, Laurence E. Turner
Bit-Serial Digital Filter Implementation using a Custom C Compiler. APCCAS (2006)
S. A. Rahim, Laurence E. Turner
A Field Programmable Bit-Serial Digital Signal Processor. IWSOC (2004)
Sean E. Krakiwsky, Laurence E. Turner, Michal M. Okoniewski
Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm. ISCAS (5) (2004)
Trevor W. Fox, Alex Carreira, Laurence E. Turner
The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. IWSOC (2003)
Alex Carreira, Trevor W. Fox, Laurence E. Turner
A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. EURASIP J. Adv. Signal Process. 2003 (6) (2003)
Trevor W. Fox, Laurence E. Turner
Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. EURASIP J. Adv. Signal Process. 2003 (6) (2003)
Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. FPGA (2002)
Alex Carreira, Trevor W. Fox, Laurence E. Turner
. FPL (2002)
Alex Carreira, Trevor W. Fox, Laurence E. Turner
A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. FPT (2002)
Trevor W. Fox, Laurence E. Turner
Low coefficient complexity approximations of the one dimensional discrete cosine transform. ISCAS (1) (2002)
Trevor W. Fox, Laurence E. Turner
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. FPL (2002)
S. G. Gibb, Laurence E. Turner
The Automatic Generation of Application Specific Processors. IWLS (2002)
Trevor W. Fox, Laurence E. Turner
The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. ISCAS (2) (2001)
T. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, Michel Fattouche
An FPGA implementation of a matched filter detector for spread spectrum communications systems. FPL (1997)
Laurence E. Turner, Peter J. W. Graumann
Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. FPL (1995)
G. Panneerselvam, Peter J. W. Graumann, Laurence E. Turner
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. FPL (1995)
Laurence E. Turner, Peter J. W. Graumann, S. G. Gibb
BIT-Serial FIR Filters with CSD Coefficients for FPGAs. FPL (1995)
Bruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner
DSP System Synthesis Including Variable Data Path Width. ISCAS (1994)
Stephen Worthington, Laurence E. Turner
A method of evaluating the effects of signal quantization at arbitrary locations in recursive digital filters. ISCAS (1993)
R. Nagalla, Laurence E. Turner
Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. VLSI (1991)
Laurence E. Turner, Peter B. Denyer, David S. Renshaw
A bit serial LDI recursive digital filter. ICASSP (1984)