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Koki Ishida
ORCID
Publication Activity (10 Years)
Years Active: 2016-2022
Publications (10 Years): 9
Top Topics
Active Stereo Vision
Processor Core
Quantum Computing
Camera Projector
Top Venues
CoRR
MICRO
IEEE Micro
ISOCC
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Publications
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Iori Ishikawa
,
Ikki Nagaoka
,
Ryota Kashima
,
Koki Ishida
,
Kosuke Fukumitsu
,
Keitaro Oka
,
Masamitsu Tanaka
,
Satoshi Kawakami
,
Teruo Tanimoto
,
Takatsugu Ono
,
Akira Fujimaki
,
Koji Inoue
Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device.
ISCAS
(2022)
Koki Ishida
,
Ilkwon Byun
,
Ikki Nagaoka
,
Kosuke Fukumitsu
,
Masamitsu Tanaka
,
Satoshi Kawakami
,
Teruo Tanimoto
,
Takatsugu Ono
,
Jangwoo Kim
,
Koji Inoue
Superconductor Computing for Neural Networks.
IEEE Micro
41 (3) (2021)
Masatoki Sugimoto
,
Daisuke Iwai
,
Koki Ishida
,
Parinya Punpongsanon
,
Kosuke Sato
Directionally Decomposing Structured Light for Projector Calibration.
CoRR
(2021)
Masatoki Sugimoto
,
Daisuke Iwai
,
Koki Ishida
,
Parinya Punpongsanon
,
Kosuke Sato
Directionally Decomposing Structured Light for Projector Calibration.
IEEE Trans. Vis. Comput. Graph.
27 (11) (2021)
Takeshi Fukaya
,
Koki Ishida
,
Akie Miura
,
Takeshi Iwashita
,
Hiroshi Nakashima
Accelerating the SpMV kernel on standard CPUs by exploiting the partially diagonal structures.
CoRR
(2021)
Koki Ishida
,
Masamitsu Tanaka
,
Ikki Nagaoka
,
Takatsugu Ono
,
Satoshi Kawakami
,
Teruo Tanimoto
,
Akira Fujimaki
,
Koji Inoue
32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic.
VLSI Circuits
(2020)
Koki Ishida
,
Ilkwon Byun
,
Ikki Nagaoka
,
Kosuke Fukumitsu
,
Masamitsu Tanaka
,
Satoshi Kawakami
,
Teruo Tanimoto
,
Takatsugu Ono
,
Jangwoo Kim
,
Koji Inoue
SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices.
MICRO
(2020)
Koki Ishida
,
Masamitsu Tanaka
,
Takatsugu Ono
,
Koji Inoue
Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing.
IEICE Trans. Electron.
(5) (2018)
Koki Ishida
,
Masamitsu Tanaka
,
Takatsugu Ono
,
Koji Inoue
Single-flux-quantum cache memory architecture.
ISOCC
(2016)