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Kecheng Ji
Publication Activity (10 Years)
Years Active: 2017-2019
Publications (10 Years): 7
Top Topics
Hit Rate
Access Latency
Response Time
Cache Misses
Top Venues
Microprocess. Microsystems
PACRIM
ACM Trans. Embed. Comput. Syst.
DATE
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Publications
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Ming Ling
,
Xiaojing Shang
,
Kecheng Ji
,
Longxing Shi
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocess. Microsystems
64 (2019)
Kecheng Ji
,
Ming Ling
,
Longxing Shi
,
Jianping Pan
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embed. Comput. Syst.
17 (4) (2018)
Kecheng Ji
,
Ming Ling
,
Longxing Shi
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocess. Microsystems
55 (2017)
Kecheng Ji
,
Ming Ling
,
Qin Wang
,
Longxing Shi
,
Jianping Pan
AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
DATE
(2017)
Kecheng Ji
,
Ming Ling
,
Yang Zhang
,
Longxing Shi
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems
50 (2017)
Qin Wang
,
Kecheng Ji
,
Ming Ling
,
Longxing Shi
A mechanistic model of memory level parallelism fed with cache miss rates.
PACRIM
(2017)
Fengying Sun
,
Kecheng Ji
,
Ming Ling
,
Longxing Shi
A trace-driven analytical model with less profiling overhead for DRAM access latencies.
PACRIM
(2017)