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Kanesan Jeevan
ORCID
Publication Activity (10 Years)
Years Active: 2013-2017
Publications (10 Years): 1
Top Topics
Wireless Communication
Vlsi Design
Cost Reduction
Electric Field
Top Venues
Appl. Soft Comput.
J. Comput. Eng.
Eng. Appl. Artif. Intell.
IET Circuits Devices Syst.
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Publications
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Abhishek Rajan
,
Kanesan Jeevan
,
Tanmoy Malakar
Weighted elitism based Ant Lion Optimizer to solve optimum VAr planning problem.
Appl. Soft Comput.
55 (2017)
Chyi-Shiang Hoo
,
Kanesan Jeevan
,
Harikrishnan Ramiah
Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs.
Int. J. Circuit Theory Appl.
43 (3) (2015)
Chyi-Shiang Hoo
,
Kanesan Jeevan
,
Harikrishnan Ramiah
Enumeration technique in very large-scale integration fixed-outline floorplanning.
IET Circuits Devices Syst.
8 (1) (2014)
Paul Ratnamahilan Polycarp Hoole
,
Sanmugasundaram Thirukumaran
,
Harikrishnan Ramiah
,
Kanesan Jeevan
,
Samuel Ratnajeevan Herbert Hoole
Ground to Cloud Lightning Flash Currents and Electric Fields: Interaction with Aircraft and Production of Ionosphere Sprites.
J. Comput. Eng.
2014 (2014)
U. Eswaran
,
Harikrishnan Ramiah
,
Kanesan Jeevan
,
Ahmed Wasif Reza
Design of wideband LTE Power amplifier with Novel Dual stage Linearizer for Mobile Wireless Communication.
J. Circuits Syst. Comput.
23 (8) (2014)
Chyi-Shiang Hoo
,
Kanesan Jeevan
,
Velappa Ganapathy
,
Harikrishnan Ramiah
Variable-Order Ant System for VLSI multiobjective floorplanning.
Appl. Soft Comput.
13 (7) (2013)
Chyi-Shiang Hoo
,
Hock-Chai Yeo
,
Kanesan Jeevan
,
Velappa Ganapathy
,
Harikrishnan Ramiah
,
Irfan Anjum Badruddin
Hierarchical congregated ant system for bottom-up VLSI placements.
Eng. Appl. Artif. Intell.
26 (1) (2013)