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Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs.

Chyi-Shiang HooKanesan JeevanHarikrishnan Ramiah
Published in: Int. J. Circuit Theory Appl. (2015)
Keyphrases
  • cost reduction
  • signal processing
  • cost savings
  • hierarchical structure
  • hierarchical tree
  • bayesian networks
  • lead time
  • vlsi design
  • high speed
  • visual attention