Junyong Deng

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 9

Top Topics

Parallel Implementations

Processor Array

Special Session

Top Venues

Publications

Junyong Deng, Shuai Liu, Xiaona Qin
Watermarking-based remote secure sequential fusion estimation under the event-triggered mechanism. J. Frankl. Inst. 361 (12) (2024)
Kangle Li, Lin Jiang, Xingjie Huang, Kun Yang, Xiaoyan Xie, Junyong Deng, Rui Shan
DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture. J. Circuits Syst. Comput. 32 (9) (2023)
Kai Zhou, Junyong Deng, Yukai Zeng
Design and Memory Access Optimization of Graph processing Processor design Based on RISC-V. AIPR (2023)
Junyong Deng, Jingwen Deng, Xiaoyan Xie, Pan Zhang, Junjie Wang, Kai Zhou
Design and Implementation of SSSP Accelerator based-on Reconfigurable and Programmable Computing Array. AIPR (2023)
Junyong Deng, Qingqing Ma, Zekun Ye
Performance Characterization of Rasterization Algorithms for Reconfigurable Graphics Processor. APSIPA ASC (2021)
Junyong Deng, Qinzhe Wu, Xiaoyan Wu, Shuang Song, Joseph Dean, Lizy Kurian John
Demystifying graph processing frameworks and benchmarks. Sci. China Inf. Sci. 63 (12) (2020)
Junyong Deng, Haoyue Wu, Rui Shan, Yiwen Fu, Xinchuang Liu, Ping Wang
NPFONoC: A Low-loss, Non-blocking, Scalable Passive Optical Interconnect Network-on-Chip Architecture. APSIPA (2019)
Qinzhe Wu, Steven Flolid, Shuang Song, Junyong Deng, Lizy K. John
Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017. IISWC (2018)
Lin Jiang, Qian Yang, Yun Zhu, Junyong Deng
A parallel implementation of deblocking filter based on video array architecture for HEVC. IGSC (2016)
Junyong Deng, Lin Jiang, Zecang Zeng
Design of Multi-phase Clock Generation and Selection Circuit for CDR. CSIE (3) (2009)