Jeferson Santiago da Silva

Publication Activity (10 Years)

Years Active: 2015-2021
Publications (10 Years): 13

Top Topics

Design Space Exploration

Heterogeneous Data

Top Venues

Publications

Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
Design Principles for Packet Deparsers on FPGAs. CoRR (2021)
Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
Design Principles for Packet Deparsers on FPGAs. FPGA (2021)
Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
Bridging the Gap: FPGAs as Programmable Switches. CoRR (2020)
Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
Bridging the Gap: FPGAs as Programmable Switches. HPSR (2020)
Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
Unleashing the Power of FPGAs as Programmable Switches. FPGA (2020)
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design. CoRR (2019)
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. FCCM (2019)
Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala
One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. ICNP (2018)
Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala
One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. CoRR (2018)
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. FPGA (2018)
Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
Extern Objects in P4: an ROHC Header Compression Scheme Case Study. NetSoft (2018)
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. CoRR (2017)
Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
Extern Objects in P4: an ROHC Compression Case Study. CoRR (2016)
Jeferson Santiago da Silva, Sergio Bampi
Area-oriented iterative method for Design Space Exploration with High-Level Synthesis. LASCAS (2015)