Jaehoon Heo

Publication Activity (10 Years)

Years Active: 2021-2024
Publications (10 Years): 9

Top Topics

Energy Efficient

Top Venues

IEEE J. Solid State Circuits

IEEE J. Emerg. Sel. Topics Circuits Syst.

VLSI Technology and Circuits

Publications

Jaehoon Heo, Jung-Hoon Kim, Wontak Han, Jaeuk Kim, Joo-Young Kim
SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning. IEEE J. Solid State Circuits 59 (8) (2024)
Seunghee Han, Seungjae Moon, Teokkyu Suh, Jaehoon Heo, Joo-Young Kim
BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing. ISCA (2024)
Sukbin Lim, Jaehoon Heo, Jinho Yang, Joo-Young Kim
A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection. CICC (2024)
Jaehoon Heo, Junsoo Kim, Sukbin Lim, Wontak Han, Joo-Young Kim
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training. IEEE J. Solid State Circuits 58 (3) (2023)
Jaehoon Heo, Yongwon Shin, Sangjin Choi, Sungwoong Yune, Jung-Hoon Kim, Hyojin Sung, Youngjin Kwon, Joo-Young Kim
PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning Workloads. ICCAD (2023)
Jung-Hoon Kim, Jaehoon Heo, Wontak Han, Jaeuk Kim, Joo-Young Kim
SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning. VLSI Technology and Circuits (2023)
Jaehoon Heo, Junsoo Kim, Wontak Han, Sukbin Lim, Joo-Young Kim
T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training. CICC (2022)
Wontak Han, Jaehoon Heo, Junsoo Kim, Sukbin Lim, Joo-Young Kim
Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, Jaehoon Heo, Joo-Young Kim
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. IEEE J. Solid State Circuits 56 (4) (2021)