Hung-Yi Huang

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 6

Top Topics

Olap Query Processing

Power Consumption

Top Venues

IEEE J. Solid State Circuits

Publications

Wei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-Hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. ISSCC (2023)
Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone. IEEE J. Solid State Circuits 56 (10) (2021)
Hung-Yi Huang, Tai-Haur Kuo
162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing. IEEE J. Solid State Circuits 55 (9) (2020)
Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo
A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3. VLSI Circuits (2020)
Shih-Hsiung Chien, Tai-Haur Kuo, Hung-Yi Huang, Hong-Bin Wang, Yi-Zhi Qiu
23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction. ISSCC (2020)
Hung-Yi Huang, Tai-Haur Kuo
210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. VLSI Circuits (2019)
Wei-Te Lin, Hung-Yi Huang, Tai-Haur Kuo
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique. IEEE J. Solid State Circuits 49 (3) (2014)