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162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing.

Hung-Yi HuangTai-Haur Kuo
Published in: IEEE J. Solid State Circuits (2020)
Keyphrases
  • power consumption
  • input data
  • routing problem
  • max csp
  • database
  • expert systems
  • ad hoc networks
  • real time
  • social networks
  • routing algorithm