Hasan Erdem Yantir

ORCID

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 18

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

ICECS

ACM Trans. Embed. Comput. Syst.

University of California, Irvine, USA (PHD)

Education History

University of California, Irvine, USA

PHD

Publications

Yunus Emre Eryilmaz, Hasan Erdem Yantir, Müstak E. Yalçin
An Open-Source eFPGA-based SoC Design for Computation Acceleration. ICECS (2023)
Mohd. Tasleem Khan, Hasan Erdem Yantir, Khaled Nabil Salama, Ahmed M. Eltawil
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Wenzhe Guo, Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Khaled Nabil Salama
Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 33 (8) (2022)
Mohammed E. Fouda, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
In-memory Associative Processors: Tutorial, Potential, and Challenges. CoRR (2022)
Mohammed E. Fouda, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
In-Memory Associative Processors: Tutorial, Potential, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
A hardware/software co-design methodology for in-memory processors. J. Parallel Distributed Comput. 161 (2022)
Muhammad Irfan, Hasan Erdem Yantir, Zahid Ullah, Ray C. C. Cheung
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs. IEEE Embed. Syst. Lett. 14 (2) (2022)
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
IMCA: An Efficient In-Memory Convolution Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 29 (3) (2021)
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
An Efficient 2D Discrete Cosine Transform Processor for Multimedia Applications. SIU (2020)
Rana A. Abdelaal, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Hasan Erdem Yantir, Ahmed M. Eltawil, Smaïl Niar, Fadi J. Kurdahi
Power optimization techniques for associative processors. J. Syst. Archit. 90 (2018)
Mohamed Ayoub Neggaz, Hasan Erdem Yantir, Smaïl Niar, Ahmed M. Eltawil, Fadi J. Kurdahi
Rapid in-memory matrix multiplication using associative processor. DATE (2018)
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
Low-Power Resistive Associative Processor Implementation Through the Multi-Compare. ICECS (2018)
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
A Two-Dimensional Associative Processor. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
A Hybrid Approximate Computing Approach for Associative In-Memory Processors. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (4) (2018)
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
Approximate Memristive In-memory Computing. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi
Efficient pulsed-latch implementation for multiport register files: work-in-progress. CASES (2017)
Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi
Process variations-aware resistive associative processor design. ICCD (2016)
Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar
Application specific multi-port memory customization in FPGAs. FPL (2014)
Hasan Erdem Yantir, Arda Yurdakul
An Efficient Heterogeneous Register File Implementation for FPGAs. IPDPS Workshops (2014)
Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs. DSD (2013)

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Publication Activity (10 Years)

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Hasan Erdem Yantir