Guiming Wu

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 6

Top Topics

Scalar Multiplication

Hardware Implementation

Hardware Architecture

Top Venues

计算机科学

ACM Trans. Reconfigurable Technol. Syst.

Publications

Pengcheng Qiu, Guiming Wu, Tingqiang Chu, Changzheng Wei, Runzhou Luo, Ying Yan, Wei Wang, Hui Zhang
MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof. IACR Cryptol. ePrint Arch. 2024 (2024)
Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yuan Zhao, Yinchao Zou, Jie Zhang, Changzheng Wei, Ying Yan, Hui Zhang
Topgun: An ECC Accelerator for Private Set Intersection. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yunfeng Shi, Xin Long, Linquan Jiang, Shuangchen Li, Yuan Xie, Changzheng Wei, Yuan Zhao, Ying Yan, Hui Zhang, Yinchao Zou
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption. IEEE Micro 43 (5) (2023)
Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Xin Long, Yuan Zhao, Yinchao Zou
A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519. FCCM (2022)
Xun Jia, Lei Qian, Guiming Wu, Dong Wu, Xianghui Xie
FPGA应用于高性能计算的研究现状和未来挑战 (Research Advances and Future Challenges of FPGA-based High Performance Computing). 计算机科学 46 (11) (2019)
Xun Jia, Guiming Wu, Xianghui Xie
A High-Performance Accelerator for Floating-Point Matrix Multiplication. ISPA/IUCC (2017)
Guiming Wu, Fang Zheng, Xianghui Xie, Dong Wu, Xinkai Yan
GF(2m)上椭圆曲线标量乘的硬件结构实现 (Hardware Implementation of Scalar Multiplication on Elliptic Curves over GF(2m)). 计算机科学 42 (1) (2015)
Guiming Wu, Miao Wang, Xianghui Xie, Yong Dou, Song Guo
面向定制结构的稀疏矩阵分块方法 (Sparse Matrix Blocking Method for Custom Architecture). 计算机科学 42 (11) (2015)
Song Guo, Yong Dou, Yuanwu Lei, Guiming Wu
A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme. IEICE Electron. Express 12 (11) (2015)
Guiming Wu, Xianghui Xie, Yong Dou, Miao Wang
High-Performance Architecture for the Conjugate Gradient Solver on FPGAs. IEEE Trans. Circuits Syst. II Express Briefs (11) (2013)
Guiming Wu, Yong Dou, Junqing Sun, Gregory D. Peterson
A High Performance and Memory Efficient LU Decomposer on FPGAs. IEEE Trans. Computers 61 (3) (2012)
Guiming Wu, Xianghui Xie, Yong Dou, Junqing Sun, Dong Wu, Yuan Li
Parallelizing sparse LU decomposition on FPGAs. FPT (2012)
Guiming Wu, Yong Dou, Miao Wang
High performance and memory efficient implementation of matrix multiplication on FPGAs. FPT (2010)
Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni
A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25 (4) (2010)
Guiming Wu, Yong Dou, Miao Wang
Automatic synthesis of processor arrays with local memories on FPGAs. FPT (2010)
Guiming Wu, Yong Dou, Gregory D. Peterson
Blocking LU Decomposition for FPGAs. FCCM (2010)
Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS (2010)
Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. FCCM (2009)
Guiming Wu, Miao Wang, Yong Dou, Fei Xia
Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms. ICPP Workshops (2009)
Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou
A coarse-grained reconfigurable computing architecture with loop self-pipelining. Sci. China Ser. F Inf. Sci. 52 (4) (2009)
Guiming Wu, Jinhui Xu, Yong Dou, Miao Wang
Computation rotating for data reuse. ACSAC (2008)
Miao Wang, Guiming Wu, Zhiying Wang
Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. ISPA (2007)
Yong Dou, Jinhui Xu, Guiming Wu
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC (2007)
Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. Asia-Pacific Computer Systems Architecture Conference (2006)