Grzegorz Blakiewicz

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 6

Top Topics

Photon Counting

Wide Dynamic Range

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Instrum. Meas.

Publications

Miron Klosowski, Yichuang Sun, Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski
Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Grzegorz Blakiewicz, Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Stanislaw Szczepanski
Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2020)
Grzegorz Blakiewicz, Jacek Jakusz, Miron Klosowski, Waldemar Jendernalik, Stanislaw Szczepanski
Light-Powered Starter for Micro-Power Boost DC-DC Converter for CMOS Image Sensors. Circuits Syst. Signal Process. 39 (3) (2020)
Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Miron Klosowski, Stanislaw Szczepanski
A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces. Sensors 20 (11) (2020)
Miron Klosowski, Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Stanislaw Szczepanski, Slawomir Koziel
A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors. IEEE Trans. Instrum. Meas. 67 (10) (2018)
Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Stanislaw Szczepanski
A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2017)
Tomasz Kulej, Grzegorz Blakiewicz
A 0.5 V bulk-driven voltage follower/DC level shifter and its application in class AB output stage. Int. J. Circuit Theory Appl. 43 (11) (2015)
Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski, Robert Piotrowski
An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2013)
Grzegorz Blakiewicz
Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower. IET Circuits Devices Syst. 5 (5) (2011)
Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Robert Piotrowski, Stanislaw Szczepanski
Analog CMOS processor for early vision processing with highly reduced power consumption. ECCTD (2011)
Grzegorz Blakiewicz
Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic. IET Circuits Devices Syst. 4 (5) (2010)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
Optimization of active circuits for substrate noise suppression. ISCAS (2008)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
Supply current spectrum estimation of digital cores at early design. IET Circuits Devices Syst. 1 (3) (2007)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
Estimation of supply current spectrum for early noise evaluation. ISCAS (2006)
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang
Substrate noise modeling in early floorplanning of MS-SOCs. ASP-DAC (2005)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
Modeling of substrate noise block properties for early prediction. ISCAS (3) (2005)
Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang
Substrate noise-aware floorplanning for mixed-signal SOCs. ISCAS (2) (2004)
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske
Substrate noise optimization in early floorplanning for mixed signal SOCs. SoCC (2004)