Faquir C. Jain

Publication Activity (10 Years)

Years Active: 2007-2019
Publications (10 Years): 4

Top Topics

Cmos Technology

Monitoring System

Prolate Spheroidal

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IET Circuits Devices Syst.

Publications

Hanfeng Wang, Samira Shamsir, Ifana Mahbub, Syed K. Islam, Allen Legassey, Raja Hari Gudlavelleti, Fotios Papadimitrakopoulos, Faquir C. Jain
Highly Linear Amperometric Glucose Detection System Realized in Deep Submicron CMOS Technology. MeMeA (2019)
Supriya Karmakar, John A. Chandy, Faquir C. Jain
Eight-bit ADC using non-volatile flash memory. IET Circuits Devices Syst. 13 (1) (2019)
Ravi Shankar R. Velampati, El-Sayed A. M. Hasaneen, E. K. Heller, Faquir C. Jain
Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Supriya Karmakar, Mukesh Gogna, Faquir C. Jain
Application of quantum dot gate nonvolatile memory (QDNVM) in image segmentation. Signal Image Video Process. 10 (3) (2016)
Santhisagar Vaddiraju, Michail Kastellorizios, Allen Legassey, Diane J. Burgess, Faquir C. Jain, Fotios Papadimitrakopoulos
Needle-implantable, wireless biosensor for continuous glucose monitoring. BSN (2015)
Supriya Karmakar, John A. Chandy, Faquir C. Jain
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Supriya Karmakar, Mukesh Gogna, Ernesto Suarez, Faquir C. Jain
Three-state quantum dot gate field-effect transistor in silicon-on-insulator. IET Circuits Devices Syst. 9 (2) (2015)
Supriya Karmakar, John A. Chandy, Faquir C. Jain
Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory. J. Signal Process. Syst. 75 (3) (2014)
Robert A. Croce, Santhisagar Vaddiraju, Allen Legassey, Yan Wang, Diane J. Burgess, Fotios Papadimitrakopoulos, Faquir C. Jain
A low power miniaturized CMOS-based continuous glucose monitoring system. BSN (2013)
Supriya Karmakar, John A. Chandy, Faquir C. Jain
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Robert A. Croce, Santhisagar Vaddiraju, Fotios Papadimitrakopoulos, Faquir C. Jain
Theoretical Analysis of the Performance of Glucose Sensors with Layer-by-Layer Assembled Outer Membranes. Sensors 12 (10) (2012)
Shuo Wang, Lei Wang, Faquir C. Jain
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation. ACM J. Emerg. Technol. Comput. Syst. 5 (1) (2009)
Jianwei Dai, Lei Wang, Faquir C. Jain
Analysis of Defect Tolerance in Molecular Crossbar Electronics. IEEE Trans. Very Large Scale Integr. Syst. 17 (4) (2009)
Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang, Faquir C. Jain
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing. ACM J. Emerg. Technol. Comput. Syst. 5 (3) (2009)
Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang, Faquir C. Jain
Programmable threshold voltage using quantum dot transistors for low-power mobile computing. ISCAS (2008)
John A. Chandy, Faquir C. Jain
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. ISMVL (2008)
Jianwei Dai, Lei Wang, Faquir C. Jain
Analysis of defect tolerance in molecular electronics using information-theoretic measures. NANOARCH (2007)
Shuo Wang, Lei Wang, Faquir C. Jain
Dynamic redundancy allocation for reliable and high-performance nanocomputing. NANOARCH (2007)