Dariusz Kania

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 17

Top Topics

Optical Music Recognition

Logic Synthesis

Discrete Fourier Transform

Top Venues

J. Circuits Syst. Comput.

Publications

Adam Opara, Marcin Kubica, Dariusz Kania
Decomposition Approaches for Power Reduction. IEEE Access 11 (2023)
Tomasz Lukaszewicz, Dariusz Kania
A Music Classification Approach Based on the Trajectory of Fifths. IEEE Access 10 (2022)
Dariusz Kania, Paulina Kania, Tomasz Lukaszewicz
Trajectory of Fifths in Music Data Mining. IEEE Access 9 (2021)
Józef Borkowski, Janusz Mroczka, Adam Matusiak, Dariusz Kania
Frequency Estimation in Interpolated Discrete Fourier Transform With Generalized Maximum Sidelobe Decay Windows for the Control of Power. IEEE Trans. Ind. Informatics 17 (3) (2021)
Tomasz Lukaszewicz, Dariusz Kania, Zenon Kidon, Krystyna Pethe-Kania
Postural Symmetry Evaluation Based on the Analysis of Temporary and Average CoP Displacements Registered During the Follow-Up Posturography. IEEE Access 7 (2019)
Józef Borkowski, Dariusz Kania
Simulation Comparison of Frequency Estimation Methods Applied for Power Control in Renewable Energy Systems. SMACD (2019)
Adam Opara, Marcin Kubica, Dariusz Kania
Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis. IEEE Access 7 (2019)
Remigiusz Wisniewski, Grzegorz Benysek, Luís Gomes, Dariusz Kania, Theodore E. Simos, Mengchu Zhou
IEEE Access Special Section: Cyber-Physical Systems. IEEE Access 7 (2019)
Marcin Kubica, Dariusz Kania, Józef Kulisz
A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs. IEEE Access 7 (2019)
Adam Opara, Marcin Kubica, Dariusz Kania
Strategy of logic synthesis using MTBDD dedicated to FPGA. Integr. 62 (2018)
Krzysztof Kajstura, Dariusz Kania
Low Power Synthesis of Finite State Machines - State Assignment Decomposition Algorithm. J. Circuits Syst. Comput. 27 (3) (2018)
Dariusz Kania, Jozef Borkowski, Janusz Mroczka
Influence of Noise on Multifrequency Signals for the Amplitude and Phase Estimation in Photovoltaic Systems with a DSP Processor. TSP (2018)
Marcin Kubica, Dariusz Kania
Area-oriented technology mapping for LUT-based logic blocks. Int. J. Appl. Math. Comput. Sci. 27 (1) (2017)
Dariusz Kania, Jozef Borkowski
Estimation methods of multifrequency signals with noise and harmonics for PV systems with a DSP processor. TSP (2017)
Marcin Kubica, Adam Opara, Dariusz Kania
Logic synthesis for FPGAs based on cutting of BDD. Microprocess. Microsystems 52 (2017)
Robert Czerwinski, Dariusz Kania
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Jozef Borkowski, Dariusz Kania
Interpolated-DFT-Based Fast and Accurate Amplitude and Phase Estimation for the Control of Power. CoRR (2016)
Dariusz Kania
Logic Decomposition for PAL-Based CPLDs. J. Circuits Syst. Comput. 24 (3) (2015)
Jozef Borkowski, Dariusz Kania, Janusz Mroczka
Interpolated-DFT-Based Fast and Accurate Frequency Estimation for the Control of Power. IEEE Trans. Ind. Electron. 61 (12) (2014)
Robert Czerwinski, Dariusz Kania
Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocess. Microsystems 36 (1) (2012)
Adam Opara, Dariusz Kania
Decomposition-based logic synthesis for PAL-based CPLDs. Int. J. Appl. Math. Comput. Sci. 20 (2) (2010)
Dariusz Kania, Adam Milik
Logic synthesis based on decomposition for CPLDs. Microprocess. Microsystems 34 (1) (2010)
Robert Czerwinski, Dariusz Kania
Synthesis of finite state machines for CPLDs. Int. J. Appl. Math. Comput. Sci. 19 (4) (2009)
Robert Czerwinski, Dariusz Kania
CPLD-oriented Synthesis of Finite State Machines. DSD (2009)
Robert Czerwinski, Dariusz Kania
State assignment and logic optimization for finite state machines. PDeS (2009)
Dariusz Kania
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. ACM Great Lakes Symposium on VLSI (2007)
Dariusz Kania, Józef Kulisz
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. J. Syst. Softw. 80 (7) (2007)
Robert Czerwinski, Dariusz Kania
State Assignment for PAL-based CPLDs. DSD (2005)
Dariusz Kania, Józef Kulisz, Adam Milik
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD (2005)
Dariusz Kania, Adam Milik, Józef Kulisz
Decomposition of Multi-Output Functions for CPLDs. DSD (2005)
Dariusz Kania
Logic synthesis of multi-output functions for PAL-based CPLDs. FPT (2002)
Dariusz Kania
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. DATE (2002)
Dariusz Kania
Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. EUROMICRO (2000)
Dariusz Kania
A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs. EUROMICRO (2000)
Dariusz Kania
Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. EUROMICRO (1999)