Chun Xue

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 2

Top Topics

Fine Granularity

Computing Power

Top Venues

Int. J. Uncertain. Fuzziness Knowl. Based Syst.

J. Syst. Archit.

Publications

Xin Gao, Chun Xue
Ridge Estimation for Uncertain Moving Average Model Under Imprecise Observations. Int. J. Uncertain. Fuzziness Knowl. Based Syst. 30 (2) (2022)
Chun Xue, Keni Qiu, Weigong Zhang, Jing Wang, Yuanchao Xu, Mengying Zhao
Data re-allocation enabled cache locking for embedded systems. J. Syst. Archit. 77 (2017)
Beiye Liu, Miao Hu, Hai Li, Yiran Chen, Chun Xue
Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems. CODES+ISSS (2013)
Meilin Liu, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha
General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size. Int. J. Comput. Their Appl. 19 (1) (2012)
Meilin Liu, Andrew McClain, Chun Xue
Optimizing Memory Cost with Loop Transformations. CATA (2011)
Meikang Qiu, Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
Energy minimization for heterogeneous wireless sensor networks. J. Embed. Comput. 3 (2) (2009)
Jingtong Hu, Chun Xue, Yi He, Edwin Hsing-Mean Sha
Reprogramming with Minimal Transferred Data on Wireless Sensor Network. MASS (2009)
Meilin Liu, Edwin Hsing-Mean Sha, Chun Xue, Meikang Qiu
Loop Fusion Technique with Minimal Memory Cost via Retiming. CATA (2009)
Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP. J. VLSI Signal Process. 46 (1) (2007)
Zili Shao, Meng Wang, Ying Chen, Chun Xue, Meikang Qiu, Laurence T. Yang, Edwin Hsing-Mean Sha
Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems. IEEE Trans. Circuits Syst. II Express Briefs (5) (2007)
Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors. RTCSA (2007)
Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping. J. VLSI Signal Process. 47 (2) (2007)
Guochen Hua, Meng Wang, Zili Shao, Hui Liu, Chun Xue
Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System. EUC (2007)
Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. DATE (2007)
Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha
Parallel Network Intrusion Detection on Reconfigurable Platforms. EUC (2007)
Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. ASAP (2006)
Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha
Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Trans. Design Autom. Electr. Syst. 11 (1) (2006)
Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha
Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network. EUC (2006)
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
Design optimization and space minimization considering timing and code size via retiming and unfolding. Microprocess. Microsystems 30 (4) (2006)
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
Loop Striping: Maximize Parallelism for Nested Loops. EUC (2006)
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. ICPADS (1) (2006)
Zili Shao, Qingfeng Zhuge, Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha, Bin Xiao
Algorithms and analysis of scheduling for loops with minimum switching. Int. J. Comput. Sci. Eng. 2 (1/2) (2006)
Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha
Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software. IEEE Trans. Computers 55 (4) (2006)
Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha
Optimizing Timing and Code Size Using Maximum Direct Loop Fusion. PDCS (2006)
Zili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha
Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks. J. Parallel Distributed Comput. 66 (9) (2006)
Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha
Efficient Assignment and Scheduling for Heterogeneous DSP Systems. IEEE Trans. Parallel Distributed Syst. 16 (6) (2005)
Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software. ITCC (1) (2005)
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs. EUC (2005)
Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha
Multi-level Loop Fusion with Minimal Code Size. PDCS (2005)
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
High-level synthesis for DSP applications using heterogeneous functional units. ASP-DAC (2005)
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
Iterational retiming: maximize iteration-level parallelism for nested loops. CODES+ISSS (2005)
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu, Edwin Hsing-Mean Sha
Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. ISPAN (2005)
Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao
Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems. IASTED PDCS (2005)
Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems. ICPADS (2) (2005)
Chun Xue, Zili Shao, Ying Chen, Edwin Hsing-Mean Sha
Optimizing DSP scheduling via address assignment with array and loop transformation. ICASSP (5) (2005)
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
Optimizing Nested Loops with Iterational and Instructional Retiming. EUC (2005)
Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao
Optimizing Address Assignment for Scheduling Embedded DSPs. EUC (2004)
Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. IPDPS (2004)
Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks. ITCC (1) (2004)